# US 8,149,619 B2 · Memory structure having volatile and non-volatile memory portions

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- Number: US 8,149,619 B2
- Document ID: US8149619B2
- Status: Granted
- Kind: B2
- Application number: 13/026,052
- Filed: 2011-02-11
- Published: 2011-06-02
- Granted: 2012-04-03
- Earliest claimed: 2008-03-20
- Assignees: Micron Technology, Inc.
- Inventors: Howard C. Kirsch; Charles Ingalls; Werner Juengling
- Web page: https://patentgrep.com/patent/US8149619B2

## CPC

- G11C 14/0018: {whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor}
- H10B 12/09: {with simultaneous manufacture of the peripheral circuit region and memory cells}
- H10B 12/36: {the transistor being a FinFET}
- H10B 43/30: characterised by the memory core region
- G11C 16/0466: {comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence)}
- H10B 12/053: {the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383)}
- H10D 30/0413: {of FETs having charge-trapping gate insulators, e.g. MNOS transistors}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/69: IGFETs having charge trapping gate insulators, e.g. MNOS transistors
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A memory array is provided that includes a transistor having two active gates sharing a source, a drain, and a channel of the transistor. One of the active gates may be coupled to a volatile memory portion of a memory cell, such as a DRAM cell, and the other active gate may be coupled to a non-volatile memory portion, for example, a charge storage node such as a SONOS cell. Methods of operating the memory array are provided that include transferring data from the volatile memory portions to the non-volatile memory portions, transferring data from the non-volatile memory portions to the volatile memory portions, and erasing the non-volatile memory portions of a row of memory cells.

## Claims

### Claim 1

A device, comprising:
a fin field-effect transistor (finFET) comprising:
a first gate configured to switchably receive a first signal that is configured to turn on the finFET;
a second gate configured to switchably receive a second signal that is configured to turn on the finFET,
wherein the first gate is coupled to a non-volatile memory, and
wherein the finFET comprises a fin disposed between the first gate and the second gate, and wherein the fin comprises a source, a drain, a channel, and a dielectric portion that extends through a width of the fin, the dielectric portion disposed between the source and the drain and adjacent to at least part of the channel.

### Claim 2

A device, comprising:
a fin field-effect transistor (finFET) comprising:
a first gate configured to switchably receive a first signal that is configured to turn on the finFET;
a second gate configured to switchably receive a second signal that is configured to turn on the finFET,
wherein the first gate is coupled to a non-volatile memory, and
wherein the finFET comprises a first layer comprising a gate oxide, a second layer, and a third layer comprising a gate oxide, wherein the first layer, second layer, and third layer are disposed adjacent to at least a portion of the channel and interposed between at least part of the source and at least part of the drain and interposed between at least part of the first gate.

### Claim 3 (depends on 2)

The device of claim 2, wherein the second layer comprises silicon nitride, nanoparticles, or a combination thereof.

### Claim 4 (depends on 1)

The device of claim 1, wherein the non-volatile memory comprises a charge storage node.

### Claim 5 (depends on 4)

The device of claim 4, wherein the non-volatile memory comprises SONOS memory.

### Claim 6 (depends on 1)

The device of claim 1, wherein the second gate is coupled to a volatile memory.

### Claim 7 (depends on 6)

The device of claim 6, wherein the volatile memory comprises a capacitive element.

### Claim 8 (depends on 7)

The device of claim 7, wherein the capacitive element is disposed on a drain of the finFET.

### Claim 9

A device, comprising:
a fin field-effect transistor (finFET) comprising:
a first gate coupled to a non-volatile memory portion;
a second gate coupled to a volatile memory portion; and
a fin disposed between the first gate and the second gate, wherein the fin comprises a source, a drain, a channel, and a dielectric portion that extends through a width of the fin, the dielectric portion disposed between the source and the drain and adjacent to at least part of the channel.

### Claim 10 (depends on 9)

The device of claim 9, wherein the non-volatile memory comprises a charge storage node.

### Claim 11 (depends on 10)

The device of claim 10, wherein the non-volatile memory comprises SONOS memory.

### Claim 12 (depends on 9)

The device of claim 9, wherein the volatile memory comprises a capacitive element.

### Claim 13 (depends on 12)

The device of claim 12, wherein the capacitive element is disposed on a drain of the finFET.