# US 8,148,964 B2 · Monolithic III-nitride power converter

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- Number: US 8,148,964 B2
- Document ID: US8148964B2
- Status: Granted
- Kind: B2
- Application number: 12/927,962
- Filed: 2010-11-29
- Published: 2011-04-28
- Granted: 2012-04-03
- Earliest claimed: 2006-12-11
- Assignees: International Rectifier Corporation
- Inventors: Michael A. Briere
- Web page: https://patentgrep.com/patent/US8148964B2

## CPC

- G05F 1/10: Regulating voltage or current (G05F1/02 takes precedence)
- H02M 3/155: using semiconductor devices only
- H02M 3/1588: {comprising at least one synchronous rectifier element (H02M3/1582, H02M3/1584 take precedence)}
- H10D 30/4755: {having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs}
- H10D 84/01: Manufacture or treatment
- H10D 84/0158: {the components including FinFETs}
- H10D 89/105: {adapted for thermal considerations}
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D 84/08: using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies
- Y02B 70/10: Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
- G05F: SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- Y02B: CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS

## Abstract

A power arrangement that includes a monolithically integrated III-nitride power stage having III-nitride power switches and III-nitride driver switches.

## Claims

### Claim 1

A power management device comprising:
a monolithic semiconductor die having a first III-nitride power semiconductor device and a second III-nitride power semiconductor device coupled to said first III-nitride power semiconductor device in a half-bridge configuration;
said half-bridge configuration including a first driver half-bridge arrangement coupled to said first III-nitride power semiconductor device, and a second driver half-bridge arrangement coupled to said second III-nitride power semiconductor device; and
said first III-nitride power semiconductor device and said second III-nitride power semiconductor device electrically isolated from each other by a barrier formed in said monolithic semiconductor die.

### Claim 2 (depends on 1)

The power management device of claim 1, wherein said first and second driver half-bridge arrangements each includes a pair of enhancement mode III-nitride switches.

### Claim 3 (depends on 1)

The power management device of claim 1, wherein said first and second driver half-bridge arrangements each includes a pair of depletion mode III-nitride switches.

### Claim 4 (depends on 1)

The power management device of claim 1, wherein said first driver half-bridge is coupled to a level shift circuit that includes a level shift capacitor, wherein said capacitor is formed on a surface of said monolithic semiconductor die.

### Claim 5 (depends on 1)

The power management device of claim 1, wherein an output node of said half-bridge configuration is coupled to a load stage that includes a driver control circuitry that generates signals for an operation of said first and second driver half-bridge arrangements.

### Claim 6 (depends on 5)

The power management device of claim 5, wherein said driver stage control circuitry generates pulse width modulation signals.

### Claim 7 (depends on 5)

The power management device of claim 5, wherein said signals are generated when an output voltage of said power stage falls outside of a pre-set range.

### Claim 8 (depends on 5)

The power management device of claim 5, wherein said signals are generated due to a load-specific condition.

### Claim 9 (depends on 8)

The power management device of claim 8, wherein said load-specific condition includes an instantaneous temperature of said load.

### Claim 10 (depends on 8)

The power management device of claim 8, wherein said load-specific condition includes a speed of said load.

### Claim 11 (depends on 1)

The power management device of claim 1, further comprising a load stage, wherein said load stage and said monolithic semiconductor die are integrated.

### Claim 12 (depends on 11)

The power management device of claim 11, wherein said load stage includes a microprocessor.

### Claim 13 (depends on 11)

The power management device of claim 11, wherein said load stage includes a memory device.