# US 8,148,799 B2 · Self-aligned bipolar transistor structure

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- Number: US 8,148,799 B2
- Document ID: US8148799B2
- Status: Granted
- Kind: B2
- Application number: 12/692,892
- Filed: 2010-01-25
- Published: 2010-05-27
- Granted: 2012-04-03
- Earliest claimed: 2006-12-01
- Assignees: National Semiconductor Corporation
- Inventors: Monir El-Diwany; Alexei Sadovnikov; Jamal Ramdani
- Web page: https://patentgrep.com/patent/US8148799B2

## CPC

- H10D 62/136: {of heterojunction BJTs (vertical heterojunction BJTs having one or more non-monocrystalline Group IV elements H10D10/861)}
- H10D 10/021: {of heterojunction BJTs [HBT]}
- H10D 10/891: {comprising lattice-mismatched active layers, e.g. SiGe strained-layer transistors}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A bipolar transistor structure comprises a semiconductor substrate having a first conductivity type, a collector region having a second conductivity type that is opposite the first conductivity type formed in a substrate active device region defined by isolation dielectric material formed in an upper surface of the semiconductor substrate, a base region that includes an intrinsic base region having the first conductivity type formed over the collector region and an extrinsic base region having the second conductivity type formed over the isolation dielectric material, and a sloped in-situ doped emitter plug having the second conductivity type formed on the intrinsic base region.

## Claims

### Claim 1

A bipolar transistor structure formed in a semiconductor substrate having a first conductivity type, the bipolar transistor structure comprising:
a collector region having a second conductivity type that is opposite the first conductivity type and that is formed in a substrate active device region defined by isolation dielectric material formed in an upper surface of the semiconductor substrate;
an epitaxial layer having a monocrystalline portion formed over the collector region and a polycrystalline region formed over the isolation dielectric material;
a sloped in-situ doped emitter plug having the second conductivity type formed on the epitaxial layer, the sloped in-situ doped emitter having an upper surface area having a first width and a lower surface area having a second width that is less than the first width wherein the sidewalls of the sloped in-situ emitter plug are continuously sloped from the upper surface to the lower surface;
dielectric spacer material formed on sidewalls of the sloped in-situ doped emitter to provide an emitter structure such that the emitter structure may be utilized to introduce dopant having the first conductivity type into portions of the epitaxial layer.

### Claim 2 (depends on 1)

The bipolar transistor structure of claim 1, and further comprising:
a base region that includes an intrinsic base region having the first conductivity type formed over the collector region and an extrinsic base region having the second conductivity type formed over dielectric isolation material.

### Claim 3 (depends on 2)

The bipolar transistor structure of claim 2, wherein the in-situ doped emitter plug comprises a lower monocrystalline silicon portion formed on the intrinsic base region and an upper polycrystalline silicon portion formed on the lower monocrystalline silicon portion.

### Claim 4 (depends on 3)

The bipolar transistor structure of claim 3, wherein the intrinsic base region and the extrinsic base region are formed from material selected from the group consisting of Si, SiGe, SiGe—C and combinations thereof.

### Claim 5 (depends on 1)

The bipolar transistor structure of claim 1, wherein the first width is about 180 nm or less and the second width is about 100-180 nm.
