# US 8,148,724 B2 · Liquid crystal display device and method of manufacturing the same

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- Number: US 8,148,724 B2
- Document ID: US8148724B2
- Status: Granted
- Kind: B2
- Application number: 12/472,098
- Filed: 2009-05-26
- Published: 2010-05-27
- Granted: 2012-04-03
- Earliest claimed: 2008-11-26
- Assignees: LG Display Co., Ltd.
- Inventors: Chang-Deok Lee; Hyung-Beom Shin; Seok Kim
- Web page: https://patentgrep.com/patent/US8148724B2

## CPC

- G02F 1/13458: {Terminal pads}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/60: wherein the TFTs are in active matrices
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A liquid crystal display device includes a gate line and a data line on a substrate crossing each other to define a pixel region; a thin film transistor in the pixel region and connected to the gate line and the data line; a pixel electrode in the pixel region and connected to the thin film transistor; and a gate pad at an end of the gate line and a data pad at an end of the data line, at least one of the gate pad and the data pad including: a pad electrode including at least one pad contact hole therein along with a passivation layer, the passivation layer on the pad electrode, at least one side of the pad contact hole having an uneven shape in plane; and a pad electrode terminal contacting inner side surfaces of the pad electrode surrounding the pad contact hole.

## Claims

### Claim 1

A liquid crystal display device, comprising:
a gate line and a data line on a substrate crossing each other to define a pixel region;
a thin film transistor in the pixel region and connected to the gate line and the data line;
a pixel electrode in the pixel region and connected to the thin film transistor; and
a gate pad at an end of the gate line and a data pad at an end of the data line, at least one of the gate pad and the data pad including:
a pad electrode including at least one pad contact hole therein along with a passivation layer in a length direction of the data pad, the passivation layer on the pad electrode, the at least one pad contact hole having an asymmetric shape with respect to a vertical axis on the pad electrode; and
a pad electrode terminal contacting inner side surfaces of the pad electrode surrounding the plurality of pad contact holes,
wherein the asymmetric shape of the at least one pad contact hole is determined based on a contact area obtained using a circumference of the at least one pad contact hole and a thickness of the pad electrode in order to reduce a contact resistance.

### Claim 2 (depends on 1)

The device according to claim 1, wherein the thin film transistor includes a first semiconductor layer, wherein the device further includes a second semiconductor layer extending from the first semiconductor layer and below the data line and the data pad electrode, and wherein a top surface of the second semiconductor layer is exposed through the at least one pad contact hole.

### Claim 3 (depends on 2)

The device according to claim 2, wherein each of the first and second semiconductor layers includes an intrinsic amorphous silicon pattern and an impurity-doped amorphous silicon pattern on the intrinsic amorphous silicon pattern.

### Claim 4 (depends on 1)

The device according to claim 1, wherein a side of the at least one pad contact hole has an uneven shape in plane, and an opposing side of each of the plurality of pad contact holes has a straight shape in plane and is located at a corresponding side of the pad electrode.

### Claim 5 (depends on 1)

The device according to claim 1, wherein the at least one pad contact hole has a multiple-bent-path shape in plane.

### Claim 6 (depends on 1)

The device according to claim 1, wherein the at least one pad contact hole has a “” shape in plane.

### Claim 7 (depends on 1)

The device according to claim 1, wherein the at least one pad contact hole has a “L” shape in plane.

### Claim 8

A method of manufacturing a liquid crystal display device, comprising:
forming a gate line and a data line on a substrate crossing each other to define a pixel region;
forming a thin film transistor in the pixel region and connected to the gate line and the data line;
forming a pixel electrode in the pixel region and connected to the thin film transistor; and
forming a gate pad at an end of the gate line and a data pad at an end of the data line, forming at least one of the gate pad and the data pad including:
forming a pad electrode including at least one pad contact hole therein along with a passivation layer, the passivation layer on the pad electrode, the at least one pad contact hole having an asymmetric shape with respect to a vertical axis on the pad electrode; and
forming a pad electrode terminal contacting inner side surfaces of the pad electrode surrounding the plurality of pad contact holes,
wherein the asymmetric shape of the at least one pad contact hole is determined based on a contact area obtained using a circumference of the at least one pad contact hole and thickness of the pad electrode in order to reduce a contact resistance.