# US 8,148,217 B2 · Semiconductor manufacturing method and semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,148,217 B2 - Document ID: US8148217B2 - Status: Granted - Kind: B2 - Application number: 13/099,587 - Filed: 2011-05-03 - Published: 2011-08-25 - Granted: 2012-04-03 - Earliest claimed: 2005-04-27 - Assignees: Kabushiki Kaisha Toshiba - Inventors: Takashi Izumida; Sanae Ito; Takahisa Kanemura - Web page: https://patentgrep.com/patent/US8148217B2 ## CPC - H10D 30/62: Fin field-effect transistors [FinFET] - H10D 30/0245: {by further thinning the channel after patterning the channel, e.g. using sacrificial oxidation on fins} - H10D 30/6706: {for preventing leakage current (TFTs characterised by the properties of the source or drain H10D30/6713)} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A method of manufacturing a semiconductor device includes forming a mask layer on a first-conductivity-type semiconductor substrate, etching the semiconductor substrate using the mask layer as a mask, thereby forming a projecting semiconductor layer, forming a first insulating layer on the semiconductor substrate to cover a lower portion of the projecting semiconductor layer, doping a first-conductivity-type impurity into the first insulating layer, thereby forming a high-impurity-concentration layer in the lower portion of the projecting semiconductor layer, forming gate insulating films on side surfaces of the projecting semiconductor layer which upwardly extend from an upper surface of the first insulating layer, and forming a gate electrode on the gate insulating films and on the first insulating film. ## Claims ### Claim 1 A method of manufacturing a semiconductor device comprising: forming a mask layer on a first-conductivity-type semiconductor substrate; etching the semiconductor substrate using the mask layer as a mask, thereby forming a projecting semiconductor layer; forming a first insulating layer on the semiconductor substrate to cover a portion of the projecting semiconductor layer, wherein the first insulating layer covers at least the portion of the side of the projecting semiconductor layer; and forming a high-impurity-concentration layer in the portion of the projecting semiconductor layer by implanting a first-conductivity-type impurity to the first insulating layer perpendicularly to the semiconductor substrate. ### Claim 2 (depends on 1) The method according to claim 1, wherein the first-conductivity-type impurity is implanted to the first insulating layer without first passing through any other layer. ### Claim 3 (depends on 1) The method according to claim 1, further comprising thermally treating the first insulating layer and the projecting semiconductor layer to diffuse the first-conductivity-type impurity, after the forming the high-impurity-concentration layer. ### Claim 4 (depends on 1) The method according to claim 1, wherein the high-impurity-concentration layer is formed below a channel region formed in the projecting semiconductor layer. ### Claim 5 (depends on 1) The method according to claim 1, further comprising etching the first insulating layer by a predetermined depth to make the high-impurity-concentration layer closer to the gate electrode, after the forming the high-impurity-concentration layer. ### Claim 6 (depends on 1) The method according to claim 1, wherein the high-impurity-concentration layer has a higher impurity concentration than a channel region formed in the projecting semiconductor layer. ### Claim 7 (depends on 1) The method according to claim 1, wherein the high-impurity-concentration layer serves as a punch-through stopper layer for suppressing occurrence of a punch-through. ### Claim 8 (depends on 1) The method according to claim 1, wherein the high-impurity-concentration layer has substantially a same peak impurity concentration as the first insulating layer after the first-conductivity-type impurity has been implanted. ### Claim 9 (depends on 1) The method according to claim 1, wherein a level at which the high-impurity-concentration layer has a peak impurity concentration is substantially identical to a level at which the first insulating layer has a peak impurity concentration. ### Claim 10 (depends on 1) The method according to claim 1, wherein the first insulating layer serves as an element isolation region for electrically isolating elements. ### Claim 11 (depends on 1) The method according to claim 1, wherein the semiconductor substrate includes a support substrate, a second insulating layer provided on the support substrate, and a semiconductor layer provided on the second insulating layer; and the projecting semiconductor layer is formed by etching the semiconductor layer. ### Claim 12 (depends on 1) The method according to claim 1, wherein the impurity is implanted into the first insulating layer by using an accelerating voltage of a predetermined value so as to have a peak concentration of the impurity positioned within the first insulating layer and not in layers positioned below the first insulating layer. ### Claim 13 (depends on 1) The method according to claim 1, wherein the impurity is implanted into the first insulating layer by using an accelerating voltage of a predetermined value so as to have a peak concentration of the impurity positioned at a quarter of a depth of the insulating layer from a top surface thereof. ### Claim 14 (depends on 1) The method according to claim 1, wherein an upper surface of the first insulating layer is lower than an upper surface of the projecting semiconductor layer. ### Claim 15 (depends on 1) The method according to claim 1, wherein the high-impurity-concentration layer has a peak impurity concentration in the projecting semiconductor layer between an upper surface of the semiconductor substrate and the upper surface of the first insulating layer. ### Claim 16 (depends on 15) The method according to claim 15, wherein an upper surface of the first insulating layer is lower than an upper surface of the projecting semiconductor layer. ### Claim 17 (depends on 1) The method according to claim 1, wherein the first-conductivity-type impurity is implanted to the first insulating layer perpendicularly to the semiconductor substrate and moved toward the portion of the projecting semiconductor layer. ### Claim 18 (depends on 17) The method according to claim 17, wherein the impurity is implanted into the first insulating layer by using an accelerating voltage of a predetermined value so as to have a peak concentration of the impurity positioned within the first insulating layer and not in layers positioned below the first insulating layer. ### Claim 19 (depends on 17) The method according to claim 17, wherein the impurity is implanted into the first insulating layer by using an accelerating voltage of a predetermined value so as to have a peak concentration of the impurity positioned at a quarter of a depth of the insulating layer from a top surface thereof. ### Claim 20 (depends on 17) The method according to claim 17, wherein an upper surface of the first insulating layer is lower than an upper surface of the projecting semiconductor layer.