# US 8,148,212 B2 · Methods of manufacturing semiconductor devices

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- Number: US 8,148,212 B2
- Document ID: US8148212B2
- Status: Granted
- Kind: B2
- Application number: 12/313,887
- Filed: 2008-11-25
- Published: 2009-05-28
- Granted: 2012-04-03
- Earliest claimed: 2007-11-28
- Assignees: Samsung Electronics Co., Ltd.
- Inventors: Moon-Sook Lee
- Web page: https://patentgrep.com/patent/US8148212B2

## CPC

- H10D 62/118: {Nanostructure semiconductor bodies}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10B 41/30: characterised by the memory core region
- H10B 41/35: with a cell select transistor, e.g. NAND
- H10D 30/0411: {of FETs having floating gates}
- H10D 30/681: {having only two programming levels (Floating gate IGFETs programmable by two single electrons H10D30/688)}
- H10D 62/121: {oriented parallel to substrates}
- Y10S 977/813: Of specified inorganic semiconductor composition, e.g. periodic table group IV-VI compositions
- Y10S 977/842: for carbon nanotubes or fullerenes
- Y10S 977/843: Gas phase catalytic growth, i.e. chemical vapor deposition
- Y10S 977/89: Deposition of materials, e.g. coating, cvd, or ald
- Y10S 977/891: Vapor phase deposition
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10B: ELECTRONIC MEMORY DEVICES
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

A plurality of nanowires is grown on a first substrate in a first direction perpendicular to the first substrate. An insulation layer covering the nanowires is formed on the first substrate to define a nanowire block including the nanowires and the insulation layer. The nanowire block is moved so that each of the nanowires is arranged in a second direction parallel to the first substrate. The insulation layer is partially removed to partially expose the nanowires. A gate line covering the exposed nanowires is formed. Impurities are implanted into portions of the nanowires adjacent to the gate line.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, the method comprising:
growing a plurality of nanowires on a first substrate in a first direction perpendicular to the first substrate;
forming an insulation layer covering the nanowires on the first substrate to define a nanowire block including the nanowires and the insulation layer;
moving the nanowire block so that each of the nanowires is arranged in a second direction parallel to the first substrate;
partially removing the insulation layer to partially expose the nanowires;
forming a gate line covering the exposed nanowires;
implanting impurities into portions of the nanowires adjacent to the gate line; and
forming a common source line (CSL), a bit line plug and a bit line, the CSL and the bit line plug making contact with the nanowires, and the bit line making contact with the bit line plug,
wherein each nanowire, a plurality of gate lines corresponding to each nanowire, the CSL, the bit line plug and the bit line define a string, and
wherein each nanowire has a length corresponding to integer times of a length of the string.

### Claim 2 (depends on 1)

The method of claim 1, further comprising, after defining the nanowire block, removing both end portions from each nanowire of the nanowire block.

### Claim 3 (depends on 1)

The method of claim 1, wherein growing the nanowires comprises forming a nanowire column having a plurality of nanowires arranged at a first distance therebetween in a third direction perpendicular to the first direction.

### Claim 4 (depends on 3)

The method of claim 3, wherein forming the nanowire column comprises forming a nanowire array having a plurality of nanowire columns arranged at a second distance therebetween in a fourth direction perpendicular to the third direction.

### Claim 5 (depends on 4)

The method of claim 4, wherein growing the nanowires comprises growing the nanowires to a length less than the second distance.

### Claim 6 (depends on 5)

The method of claim 5, wherein defining the nanowire block comprises removing a portion of the insulation layer having a first width in the third direction to form a plurality of nanowire blocks, each of which includes one nanowire column and an insulation layer pattern.

### Claim 7 (depends on 1)

The method of claim 1, further comprising, after growing the nanowires, sequentially forming a tunnel insulation layer, a charge storing layer and a blocking layer enclosing the nanowires.

### Claim 8 (depends on 1)

The method of claim 1, wherein partially removing the insulation layer comprises forming an opening having a second width in a fifth direction perpendicular to the second direction.

### Claim 9 (depends on 1)

The method of claim 1, wherein moving the nanowire block comprises moving the nanowire block onto a second substrate, each of the nanowires extending in a sixth direction parallel to the second substrate.

### Claim 10

A method of manufacturing a semiconductor device, the method comprising:
growing a plurality of nanowires on a first substrate in a first direction perpendicular to the first substrate;
forming an insulation layer covering the nanowires on the first substrate to define a nanowire block including the nanowires and the insulation layer;
moving the nanowire block so that each of the nanowires is arranged in a second direction parallel to the first substrate;
partially removing the insulation layer to partially expose an outer surface of the nanowires, wherein partially removing the insulation layer comprises forming an opening in the nanowire block, the opening having a second width in a direction perpendicular to the second direction;
forming a gate line covering the exposed nanowires;
implanting impurities into portions of the nanowires adjacent to the gate line; and
forming a common source line (CSL), a bit line plug and a bit line, the CSL and the bit line plug making contact with the nanowires, and the bit line making contact with the bit line plug,
wherein each nanowire, a plurality of gate lines corresponding to each nanowire, the CSL, the bit line plug and the bit line define a string,
and wherein each nanowire has a length corresponding to integer times of a length of the string.

### Claim 11 (depends on 10)

The method of claim 10, wherein growing the nanowires comprises forming a nanowire column having a plurality of nanowires arranged at a first distance therebetween in a third direction perpendicular to the first direction.

### Claim 12 (depends on 10)

The method of claim 10, wherein forming the nanowire column comprises forming a nanowire array having a plurality of nanowire columns arranged at a second distance therebetween in a fourth direction perpendicular to the third direction.

### Claim 13 (depends on 12)

The method of claim 12, wherein growing the nanowires comprises growing the nanowires to a length less than the second distance.

### Claim 14 (depends on 12)

The method of claim 12, wherein defining the nanowire block comprises removing a portion of the insulation layer having a first width in the third direction to form a plurality of nanowire blocks, each of which includes one nanowire column and an insulation layer pattern.

### Claim 15 (depends on 10)

The method of claim 10, further comprising, after growing the nanowires, sequentially forming a tunnel insulation layer, a charge storing layer and a blocking layer enclosing the nanowires.

### Claim 16 (depends on 10)

The method of claim 10, further comprising, after defining the nanowire block, removing both end portions of each nanowire.

### Claim 17 (depends on 10)

The method of claim 10, wherein moving the nanowire block comprises moving the nanowire block onto a second substrate, each of the nanowires extending in a sixth direction parallel to the second substrate.