Security management in multi-node, multi-processor platforms
AssigneeIntel Corporation
InventorsMahesh S. Natu, Sham Datta
Life of this patent
Estimating the term…
Abstract
Multi-node and multi-processor security management is described in this application. Data may be secured in a TPM of any one of a plurality of nodes, each node including one or more processors. The secured data may be protected using hardware hooks to prevent unauthorized access to the secured information. Security hierarchy may be put in place to protect certain memory addresses from access by requiring permission by VMM, OS, ACM or processor hardware. The presence of secured data may be communicated to each of the nodes to ensure that data is protected. Other embodiments are described.
Claims7
A method for security in a multi-CPU computer system, comprising:
- providing a plurality of nodes, each node including:
- a trusted platform module,
- at least one CPU, and
- a node controller;
- establishing one of the plurality of nodes as a primary node;
- and
- broadcasting a security command from the primary node to the trusted platform module within each of the plurality of nodes, wherein the security command is associated with secret data stored at a secured register address within a first sub-range of secured register addresses, wherein registers within the first sub-range of secured register addresses are protected from improper access by hardware adapted to perform a privilege check, and registers within a second sub-range of secured register addresses can only be accessed:
- (i) by processor hardware, and (ii) by an Authenticated Code Module (ACM) authorized by the processor hardware, and (iii) by a Virtual Machine Monitor (VMM) authorized by both the processor hardware and the ACM, and (iv) an Operating System (OS) authorized by all of the processor hardware, the ACM, and the VMM.
Dependencies are inferred from the claim text.