System and method for enabling micro-partitioning in a multi-threaded processor

A computer program product stored on computer storage containing instructions for execution by a computer, which, when executed by the computer, cause the computer to implement a method of processing jobs, the method comprising:

• loading a first job initiated by a first partition onto a first hardware thread, the first partition including a first subset of processor resources in a processor;
• loading a second job initiated by a second partition onto a second hardware thread, the second partition including a second subset of processor resources in the processor;
• translating a first concatenated virtual address into a first system-wide real address, wherein the first concatenated virtual address includes a first virtual page identifier and a first partition identifier, the first partition identifier identifying the first partition;
• translating a second concatenated virtual address into a second system-wide real address, wherein the second concatenated virtual address includes a second virtual page identifier and a second partition identifier, the second partition identifier identifying the second partition;
• and
• simultaneously executing the first job on the first hardware thread using the first system-wide real address and the second job on the second hardware thread using the second system-wide real address, wherein the first hardware thread and the second hardware thread are co-located on the processor.

An information handling system comprising:

• one or more processors;
• a memory accessible by the processors;
• one or more nonvolatile storage devices accessible by the processors;
• and a set of instructions stored in the memory, wherein one or more of the processors executes the set of instructions in order to perform actions of:
• loading a first job initiated by a first partition onto a first hardware thread, the first partition including a first subset of processor resources in a processor;
• loading a second job initiated by a second partition onto a second hardware thread, the second partition including a second subset of processor resources in the processor;
• translating a first concatenated virtual address into a first system-wide real address, wherein the first concatenated virtual address includes a first virtual page identifier and a first partition identifier, the first partition identifier identifying the first partition;
• translating a second concatenated virtual address into a second system-wide real address, wherein the second concatenated virtual address includes a second virtual page identifier and a second partition identifier, the second partition identifier identifying the second partition;
• and
• simultaneously executing the first job on the first hardware thread using the first system-wide real address and the second job on the second hardware thread using the second system-wide real address, wherein the first hardware thread and the second hardware thread are co-located on the processor.