Dynamically controlling a prefetching range of a software controlled cache

A computer program product comprising a non-transitory computer readable medium storing a computer readable program recorded thereon, wherein the computer readable program, when executed on a computing device, causes the computing device to:

• receive source code that is to be compiled;
• analyze the source code to identify at least one of a plurality of loops that contain irregular memory references;
• for each irregular memory reference, determine whether the irregular memory reference within the at least one of the plurality of loops is a candidate for optimization;
• responsive to an indication that the irregular memory reference may be optimized, determine whether the irregular memory reference is valid for prefetching;
• responsive to an indication that the irregular memory reference is valid for prefetching, insert a store statement for an address of the irregular memory reference into the at least one of the plurality of loops;
• and
• insert a runtime library call into a prefetch runtime library to dynamically prefetch the irregular memory references associated with the at least one of the plurality of loops, wherein data associated with the irregular memory references are dynamically prefetched into a software controlled cache when the runtime library call is invoked and wherein the irregular memory references are dynamically prefetched for a lower boundary to an upper boundary of the at least one of the plurality of loops.

An apparatus, comprising:

• a processor;
• and
• a memory coupled to the processor, wherein the memory comprises instructions which, when executed by the processor, cause the processor to:
• receive source code that is to be compiled;
• analyze the source code to identify at least one of a plurality of loops that contain irregular memory references;
• for each irregular memory reference, determine whether the irregular memory reference within the at least one of the plurality of loops is a candidate for optimization;
• responsive to an indication that the irregular memory reference may be optimized, determine whether the irregular memory reference is valid for prefetching;
• responsive to an indication that the irregular memory reference is valid for prefetching, insert a store statement for an address of the irregular memory reference into the at least one of the plurality of loops;
• and
• insert a runtime library call into a prefetch runtime library to dynamically prefetch the irregular memory references associated with the at least one of the plurality of loops, wherein data associated with the irregular memory references are dynamically prefetched into a software controlled cache when the runtime library call is invoked and wherein the irregular memory references are dynamically prefetched for a lower boundary to an upper boundary of the at least one of the plurality of loops.