US 8,146,041 B1 · Latch based optimization during implementation of circuit designs for programmable logic devices

Abstract

A computer-implemented method of implementing a circuit design within a programmable logic device can include selecting at least one circuit element of the circuit design. The selected circuit element can be converted to a latch. A timing analysis can be performed upon the circuit design after conversion of the selected circuit element to a latch. A determination can be made by a computer as to whether the timing of the circuit design improves and the conversion of the selected circuit element to a latch can be accepted when the timing of the circuit design improves. The circuit design can be output.

Claims10

Dependent claims

A computer-implemented method of implementing a circuit design within an integrated circuit, the method comprising:

converting at least one circuit element of the circuit design to a latch;
determining, by a computer, whether a result of a cost function of the circuit design is reduced in consequence of converting the at least one circuit element of the circuit design to a latch;
wherein determining whether the result of the cost function is reduced comprises determining whether a number of look-up tables of the circuit design is reduced by converting the circuit element to a latch;
accepting conversion of the at least one circuit element to a latch when the result of the cost function is reduced;
and
outputting the circuit design by the computer.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application

13/180,782Filed 12 Jul 2011 · division

Priority

28 May 2008

Granted

27 Mar 2012

Term ends

Not estimatedThe source records don’t support an estimate.

Classification5 codes

G06F 30/3315
Design verification, e.g. functional simulation or model checking: using static timing analysis [STA]
G06F 30/327
Circuit design at the digital level: logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
G06F 30/3312
Using simulation: timing analysis
G06F 2119/12
Details relating to the type or aim of the analysis or the optimisation: timing analysis or timing optimisation

Latch based optimization during implementation of circuit designs for programmable logic devices

Life of this patent

Latch based optimization during implementation of circuit designs for programmable logic devices

Life of this patent

Abstract

Claims10