Method for conjecturing effective width and effective length of gate

A method for conjecturing an effective width and an effective length of a gate by using a computer, comprising:

• providing a first design gate group comprising a first gate design width and a first gate length;
• measuring a first measured inversion capacitance of said first design gate group under an inversion voltage to calculate an intrinsic gate channel capacitance of said first design gate group;
• measuring a zero capacitance of said first design gate group under a zero gate voltage to calculate an edge capacitance of said first design gate group;
• predicting a first width error by means of said intrinsic gate channel capacitance and of said edge capacitance to calculate a calculated inversion capacitance of a first width and a predicted first width deviation;
• repeatedly predicting said first width error to minimize said predicted first width deviation and to optimize the first width error to obtain an optimized first width error;
• predicting a first length error by means of said intrinsic gate channel capacitance and of said edge capacitance to calculate a calculated inversion capacitance of a first length and a predicted first length deviation;
• repeatedly predicting said first length error to minimize said predicted first length deviation and to optimize the first length error to obtain an optimized first length error;
• and
• conjecturing said effective width and said effective length of said first design gate group by means of said optimized first width error and said optimized first length error.