US 8,146,034 B2 · Efficient Redundancy Identification, Redundancy Removal, and Sequential Equivalence Checking within Designs Including Memory Arrays.

Abstract

A mechanism is provided for efficient redundancy identification, redundancy removal, and sequential equivalence checking with designs including memory arrays. The mechanism includes an array merging component to optimally merge an array output such that if the address is out-of-bounds or the port is not asserted, the array output is converted to a random output. The mechanism also includes a component for determining the equivalence of enabled array outputs rather than the array outputs directly and creating an enabled array output. The mechanism also includes a component that precludes potentially-redundant array cells from participating in the sequential redundancy removal determination. This component first checks for compatibility of the corresponding arrays, then the corresponding read port enables and addresses, then the corresponding initial values, and finally checking that writes to the corresponding columns yield a compatible set of values.

Claims20

Dependent claims

A method, in a data processing system, for performing redundancy removal in an integrated circuit design with a memory array, the method comprising:

receiving, by the data processing system, a netlist for an integrated circuit design, wherein the netlist comprises a memory array having one or more arrayouts;
determining, by the data processing system, an equivalent class comprising a set of suspected equivalent gates, wherein the set of suspected equivalent gates comprises a plurality of arrayouts;
determining, by the data processing system, whether a first arrayout and a second gate in the equivalence class are equivalent;
and
responsive to the first arrayout and the second gate being equivalent, merging, by the data processing system, the first arrayout and the second gate.

2 more elements

A computer program product comprising a computer readable storage medium having a computer readable program stored therein, wherein the computer readable program, when executed on a computing device, causes the computing device to:

receive, by the computing device, a netlist for an integrated circuit design, wherein the netlist comprises a memory array having one or more arrayouts;
determine, by the computing device, an equivalent class comprising a set of suspected equivalent gates, wherein the set of suspected equivalent gates comprises a plurality of arrayouts;
determine, by the computing device, whether a first arrayout and a second gate in the equivalence class are equivalent;
and
responsive to the first arrayout and the second gate being equivalent, merge, by the computing device, the first arrayout and the second gate.

2 more elements

Dependencies are inferred from the claim text.

Efficient Redundancy Identification, Redundancy Removal, and Sequential Equivalence Checking within Designs Including Memory Arrays.

Life of this patent

Efficient Redundancy Identification, Redundancy Removal, and Sequential Equivalence Checking within Designs Including Memory Arrays.

Life of this patent

Abstract

Claims20