US 8,146,031 B2Granted

Method for generating and evaluating a table model for circuit simulation

AssigneeTexas Instruments Incorporated

InventorGang Peter Fang

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Abstract

A method for generating and evaluating a table model for circuit simulation in N dimensions employing mathematical expressions for modeling a device. The table model uses an unstructured N-dimensional grid for approximating the expressions. The method includes the steps of: (a) establishing a function domain having boundary limits in the N dimensions; (b) performing an accuracy partitioning operation to establish accuracy partitions; the mathematical expressions being satisfied within each accuracy partition within a predetermined error criteria; (c) performing a continuity partitioning operation to establish continuity partitions ensuring continuity of solutions of the mathematical expressions across boundaries separating adjacent accuracy partitions; (d) performing a grid refining operation to configure the continuity partitions to assure monotonic solutions of the mathematical expressions in the continuity partitions; (e) if a continuity partition is altered during the grid refining operation, returning to step (c), else proceeding to next step; (f) ending the method.

Claims1

Dependent claims

A method for a digital processor of obtaining a function value of tree based device table model for a circuit simulation, comprising:

(a) determining at the digital processor if a current bias voltage point is at least one of inside or outside a last visited leaf partition;
(b) at least one of proceeding to step (e), if the bias voltage point is in inside the last visited leaf partition;
or, determining if the current partition is in an immediate parent node partition, if the current bias voltage point is outside the last visited leaf partition;
(c) at least one of repeating step (b), if the current bias voltage point is not in the parent node partition;
or, searching for a child partition of the immediate parent node partition relevant to the current bias voltage point, if the current bias voltage point is in the immediate parent node partition;
(d) determining if the child partition is a leaf and repeating step (c) if the child partition is not a leaf and proceeding to step (e) if the child partition is a leaf;
and
(e) performing multi-linear interpolation for determining the bias voltage values while reserving continuity and monotonic of continuous and monotonic function of multiple variables.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/328,595Filed 4 Dec 2008 · continuation
Priority: 18 Nov 2004
Published: US 2009/0099831 A116 Apr 2009
Granted: 27 Mar 2012
Term ends: Not estimatedThe source records don’t support an estimate.

Classification3 codes

G06F 30/3323
Design verification, e.g. functional simulation or model checking: using formal methods, e.g. equivalence checking or property checking
G06F 30/33
Circuit design at the digital level: design verification, e.g. functional simulation or model checking
G06F
Computing and data processing

Family

Application10/992,140Parent of this continuation · filed 18 Nov 2004
US 2009/0099831 A1Pre-grant publication · published 16 Apr 2009
US 7,493,575 B2Parent of this continuation
US 2006/0015304 A1Published application
US 8,146,031 B2This patent

From the US filing history. Foreign family members aren’t listed.