US 8,145,981 B2 · Soft bit data transmission for error correction control in non-volatile memory

Abstract

Data stored in non-volatile storage is decoded using iterative probabilistic decoding. An error correcting code such as a low density parity check code may be used. In one approach, initial reliability metrics, such as logarithmic likelihood ratios, are used in decoding sensed states of a set of non-volatile storage element. The decoding attempts to converge by adjusting the reliability metrics for bits in code words which represent the sensed state. Soft data bits are read from the memory if the decoding fails to converge. Initial reliability metric values are provided after receiving the hard read results and at each phase of the soft bit operation(s). In one embodiment, a second soft bit is read from the memory using multiple subsets of soft bit compare levels. While reading at the second subset of compare levels, decoding can be performed based on the first subset data.

Claims19

Dependent claims

A method of reading non-volatile storage, comprising:

providing a set of read compare points for a plurality of non-volatile storage elements as part of an error correction control process while reading a first set of data from the storage elements, the set of read compare points including a first subset of read compare points having one read compare point corresponding to each programmable state of the storage elements and a second subset of read compare points having one read compare point corresponding to each programmable state of the storage elements, wherein providing includes providing the first subset prior to the second subset;
determining a second set of data based on the first subset of read compare points;
and
iteratively decoding the first set of data using the second set of data while providing the second subset of read compare points for the plurality of non-volatile storage elements.

1 more element

A non-volatile memory system, comprising:

a plurality of non-volatile storage elements;
and
managing circuitry in communication with the set of non-volatile storage elements, the managing circuitry performs one or more operations that include:
providing a set of read compare points for the plurality of non-volatile storage elements as part of an error correction control process while reading a first set of data from the storage elements, the set of read compare points including a first subset of read compare points having one read compare point corresponding to each programmable state of the storage elements and a second subset of read compare points having one read compare point corresponding to each programmable state of the storage elements, wherein providing includes providing the first subset prior to the second subset,
determining a second set of data based on the first subset of read compare points, and
iteratively decoding the first set of data using the second set of data while providing the second subset of read compare points for the plurality of non-volatile storage elements.

3 more elements

Dependencies are inferred from the claim text.

Soft bit data transmission for error correction control in non-volatile memory

Life of this patent

Soft bit data transmission for error correction control in non-volatile memory

Life of this patent

Abstract

Claims19