Scan test circuit and scan test control method

A semiconductor integrated circuit, comprising:

• a control flip-flop for inputting a scan control signal;
• and
• a scan path chain including a plurality of scan storage elements serially connected to each other, the scan path chain performing a shift operation as a first mode when an output of the control flip-flop is a first status value, and performing a normal operation as a second mode when an output of the control flip-flop is a second status value, wherein,
• when the scan control signal is switched from the first status value to the second status value, the control flip-flop outputs the second status value to the plurality of scan storage elements in synchronization with a first clock pulse, after the switching, of a clock provided to the plurality of scan storage elements, and,
• when the scan control signal is switched from the second status value to the first status value, the control flip-flop outputs the first status value to the plurality of scan storage elements at a timing of the scan control signal switching.