Semiconductor integrated circuit device and delay fault testing method thereof
AssigneeKabushiki Kaisha Toshiba
InventorsKeiko Fukuda, Yoshinori Watanabe, Ryouichi Bandai
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Abstract
A semiconductor integrated circuit device includes a first clock domain having a plurality of first flip-flops which is configured to operate with a high-speed clock; a second clock domain having a plurality of second flip-flops, composed of a third flip-flop and a plurality of fourth flip-flops, which is configured to operate with a low-speed clock; and a test clock supplying section configured to supply, at a time of delay fault test for the second clock domain, a test clock based on the high-speed clock to the third flip-flop to which data from the first clock domain is input, and not to supply the test clock to the plurality of fourth flip-flops.
Claims17
A semiconductor integrated circuit device, comprising:
- a first clock domain in which a plurality of first flip-flops are provided on a data path, and which is configured to operate with a first clock;
- a second clock domain in which a plurality of second flip-flops are provided on a data path, and which is configured to operate with a second clock of a lower frequency than a frequency of the first clock;
- a first test clock supplying section configured to supply a test clock based on the first clock to all of the first flip-flops at a time of a delay fault test;
- and
- a second test clock supplying section configured to supply, at the time of the delay fault test, a test clock based on the first clock to a third flip-flop to which data from the first clock domain is input among the plurality of second flip-flops, and not to supply the test clock to a plurality of fourth flip-flops excluding the third flip-flop among the plurality of second flip-flops.
A delay fault testing method of a semiconductor integrated circuit device comprising a first clock domain in which a plurality of first flip-flops are provided on a data path and which is configured to operate with a first clock, and a second clock domain in which a plurality of second flip-flops are provided on a data path and which is configured to operate with a second clock of a lower frequency than a frequency of the first clock, in which the plurality of second flip-flops have a third flip-flop into which data from the first clock domain is input and a plurality of fourth flip-flops other than the third flip-flop among the plurality of second flip-flops, the method comprising:
- in a transfer period of the delay fault test, supplying a third clock of a frequency that is less than or equal to a frequency of the second clock to all of the first and second flip-flops;
- and
- in a transition period of the delay fault test, supplying a test clock based on the first clock to all of the flip-flops excluding the fourth flip-flops among the first and second flip-flops.
Dependencies are inferred from the claim text.