Systems and methods for measuring soft errors and soft error rates in an application specific integrated circuit

A method for measuring soft errors in an application specific integrated circuit (ASIC), the method comprising:

• accessing a scan chain on the ASIC to write initial data into the individual storage elements within the scan chain, wherein accessing comprises writing a first data pattern into a set of test control registers and writing a second data pattern into the individual storage elements of the scan chain;
• arranging the ASIC in registration with an emitter configured to generate and direct a neutron flux in the direction of the ASIC;
• exposing the ASIC to the neutron flux to trigger a soft error in one or more storage elements within the scan chain;
• accessing the contents of the set of control registers and comparing read data values to the first data pattern, when the comparing results in an indication that the read data values do not match the first data pattern, ignoring data from the individual storage elements of the scan chain, when the comparing indicates that read data values match the first data pattern, storing the contents of the individual storage elements of the scan chain in a first array while writing an alternating data pattern into the individual storage elements of the scan chain;
• accessing the contents of the set of control registers and comparing read data values to the first data pattern, when the comparing results in an indication that the read data values do not match the first data pattern, verifying a latch condition, when the comparing indicates that read data values match the first data pattern, storing the contents of the individual storage elements of the scan chain in a second array while writing a new baseline data pattern into the individual storage elements of the scan chain;
• comparing the second data pattern with the contents of the first array;
• and
• comparing the alternating data pattern with the contents of the second array.