Clock signal generator for generating stable clock signal, semiconductor memory device including the same, and methods of operating
AssigneeSamsung Electronics Co., Ltd.
InventorsSung Geun Park, Chul Joon Choi, Hyuk Jun Sung, Byung Yoon Kang
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Abstract
A clock signal generator can include a clock signal generation unit that is configured to generate a clock signal. A clock signal control unit is configured to count a number of pulses of the clock signal during a reference time, and to compare the number of pulses with a reference value to provide a comparison result, and to generate a control signal based on the comparison result, where the clock signal generation unit increases or decreases the number of pulses of the clock signal based on the control signal.
Claims9
A clock signal generator comprising:
- a clock signal generation unit configured to generate a clock signal;
- and
- a clock signal control unit configured to count a number of pulses of the clock signal during a reference time, compare the number of pulses with a reference value to provide a comparison result, and generate a control signal based on the comparison result,
- wherein the clock signal generation unit increases or decreases the number of pulses of the clock signal based on the control signal, wherein the reference value comprises a re-programmable reference value stored in the clock signal control unit responsive to a host command from a host,
- wherein the reference time is a period of time from reception of a first start-of-frame signal transmitted from the host through a universal serial bus to reception of a second start-of-frame signal transmitted from the host after the first start-of-frame signal.
A method of generating a clock signal, comprising:
- generating a clock signal;
- programming a reference value into a storage location responsive to a host command;
- counting a number of pulses of the clock signal during a reference time;
- comparing the number of pulses with the reference value to provide a comparison result;
- and
- generating a control signal based on the comparison result, wherein the number of pulses of the clock signal is increased or decreased based on the control signal, wherein the reference time is a period of time from reception of a first start-of-frame signal transmitted from the host through a universal serial bus to reception of a second start-of-frame signal transmitted from the host after the first start-of-frame signal.
A semiconductor memory device comprising:
- a clock signal generator configured to generate a clock signal;
- and
- a central processing unit configured to transmit data to and receive data from a host through a universal serial bus based on the clock signal,
- wherein the clock signal generator counts the number of pulses of the clock signal during a reference time, compares a counting result with a reference value, and increases or decreases the number of pulses of the clock signal based on a comparison result, wherein the reference value comprises a re-programmable reference value stored in the memory device responsive to a host command from the host, wherein the reference time is a period of time from reception of a first start-of-frame signal transmitted from the host through the universal serial bus to reception of a second start-of-frame signal transmitted from the host after the first start-of-frame signal.
A method of transmitting and receiving data, comprising:
- generating a clock signal;
- programming a reference value into a storage location responsive to a host command from a host;
- transmitting data to and receiving data from the host through a universal serial bus based on the clock signal,
- wherein the number of pulses of the clock signal is increased or decreased based on a result of comparing the number of pulses of the clock signal counted during a reference time with the reference value, wherein the reference time is a period of time from reception of a first start-of-frame signal transmitted from the host through a universal serial bus to reception of a second start-of-frame signal transmitted from the host after the first start-of-frame signal.
Dependencies are inferred from the claim text.