Pipelined microprocessor with fast conditional branch instructions based on static microcode-implemented instruction state

A method for fast execution of a conditional branch instruction by a microprocessor, the method comprising:

• storing in a memory instructions of a non-user program to implement a user program instruction of the user-visible instruction set of the microprocessor, the non-user program including a conditional branch instruction;
• fetching instructions of the user program that includes the instruction that is implemented by the non-user program, wherein said fetching is performed by a first fetch unit of the microprocessor;
• decoding the user program instructions;
• saving a state in response to decoding the user program instruction that is implemented by the non-user program;
• executing the user program instructions fetched by the first fetch unit and configured to execute instructions of the non-user program other than the conditional branch instruction, wherein said executing is performed by an execution unit of the microprocessor;
• fetching the non-user program instructions from the memory;
• and
• resolving the conditional branch instruction based on the saved state without sending the conditional branch instruction to the execution unit to resolve the conditional branch instruction, wherein said fetching the non-user program instructions and said resolving the conditional branch instruction are performed by a second fetch unit of the microprocessor.

A computer program product for use with a computing device, the computer program product comprising:

• a computer usable storage medium, having computer readable program code embodied in said medium, for specifying a microprocessor, the computer readable program code comprising:
• first program code for specifying a memory, configured to store instructions of a non-user program to implement a user program instruction of the user-visible instruction set of the microprocessor, the non-user program including a conditional branch instruction;
• second program code for specifying a first fetch unit, configured to fetch instructions of the user program that includes the instruction that is implemented by the non-user program;
• third program code for specifying an instruction decoder, configured to decode the user program instructions and to save a state in response to decoding the user program instruction that is implemented by the non-user program;
• fourth program code for specifying an execution unit, configured to execute the user program instructions fetched by the first fetch unit, and configured to execute instructions of the non-user program other than the conditional branch instruction;
• and
• fifth program code for specifying a second fetch unit, configured to fetch the non-user program instructions from the memory, and configured to resolve the conditional branch instruction based on the saved state without sending the conditional branch instruction to the execution unit to resolve the conditional branch instruction.