Data processing system with branch target addressing using upper and lower bit permutation

A data processor comprising:

• an instruction decoder for decoding an instruction;
• and
• an execution unit for executing an instruction on the basis of a result of decoding of the instruction decoder,
• the execution unit configured to execute a data transfer instruction before execution of a branch instruction,
• wherein the data transfer instruction is an instruction for reading a memory and storing read data of N bits to a lower-order side of a first register of 2N bits, N being an integer, and
• wherein the branch instruction is an instruction for obtaining a branch address having a length of 2N bits, the data of N bits stored on the lower-order side of the first register designated by the branch instruction is set to lower N bits of the branch address regardless of data of lower N bits of a program counter, and data of upper N bits of the program counter is set to upper N bits of the branch address regardless of data of N bits stored on the remaining upper-order side of the first register.