Data processing circuit with a plurality of instruction modes, method of operating such a data circuit and scheduling method for such a data circuit

A method of scheduling operations for a programmable data processor that is operable to execute programs under the control of time-stationary instructions in a plurality of different instruction modes, each instruction mode defining a respective assignment of fields of instructions to selection of operations and selection of result registers, the method comprising:

• receiving an input program defining operations;
• assigning instruction modes to respective parts of the input program;
• assigning result registers to the operations that arise from the input program;
• assigning operations arising from the input program to sequential instruction locations in a target program, under a constraint that operations from each selected part are assigned to a respective range of instruction locations, the respective ranges for different parts having no mutual overlap;
• inserting operation selection codes for selecting the operations each into a first field of a respective instruction at the assigned location for the operation;
• inserting mode change commands into instructions of the target program located such that the mode change commands take effect at borders between the ranges;
• and
• inserting result register address selection codes into second fields of the instructions of the target program at offsets relative to the instructions into which corresponding selection codes are inserted, the offsets corresponding to a number of instruction cycles needed for generating a result with the operation selected by the corresponding selection code.

A computer configured to schedule operations for a programmable data processor that is operable to execute programs under control of time-stationary instructions in a plurality of different instruction modes, each instruction mode defining a respective assignment of fields of instructions to selection of operations and selection of result registers, the computer comprising:

• a processor for executing computer-executable instructions;
• and
• a non-transitory computer-readable medium comprising computer-executable instructions that, when executed by the processor, cause the computer to carry out steps comprising:
• receiving an input program defining operations;
• assigning instruction modes to respective parts of the input program;
• assigning result registers to the operations that arise from the input program;
• assigning operations arising from the input program to sequential instruction locations in a target program, under a constraint that operations from each selected part are assigned to a respective range of instruction locations, the respective ranges for different parts having no mutual overlap;
• inserting operation selection codes for selecting the operations each into a first field of a respective instruction at the assigned location for the operation;
• inserting mode change commands into instructions of the target program located such that the mode change commands take effect at borders between the ranges;
• and
• inserting result register address selection codes into second fields of the instructions of the target program at offsets relative to the instructions into which corresponding selection codes are inserted, the offsets corresponding to a number of instruction cycles needed for generating a result with the operation selected by the corresponding selection code.