Enhanced load lookahead prefetch in single threaded mode for a simultaneous multithreaded microprocessor

A computer program product comprising a non-transitory computer-readable medium having a computer readable program stored therein, wherein the computer readable program, when executed in a data processing system, causes the data processing system to:

• detect if a long-latency miss associated with a load instruction has been encountered by a processing unit, wherein the processing unit is operating in a single threaded mode;
• responsive to the encounter of the long-latency miss, enter a load lookahead mode in the processing unit;
• responsive to entering the load lookahead mode:
• dispatch each instruction from a first set of instructions from a first buffer with an associated vector, wherein the associated vector is within a set of vectors in a first vector array;
• responsive to entering the load lookahead mode, fetch additional instructions into the first buffer in order until the first buffer is full;
• responsive to filling the first buffer, fetch the additional instructions into a second buffer in order until the second buffer is full;
• and
• responsive to filling the second buffer, stop the fetch of the additional instructions;
• determine whether the first set of instructions from the first buffer have completed execution;
• and
• responsive to completed execution of the first set of instructions from the first buffer:
• copy the set of vectors from the first vector array to a second vector array;
• and
• dispatch a second set of instructions from the second buffer with an associated vector from the second vector array.

A system, comprising:

• a processing unit;
• and
• a memory coupled to the processing unit, wherein the memory comprises instructions which, when executed by the processing unit, cause the processing unit to:
• detect if a long-latency miss associated with a load instruction has been encountered, wherein the processing unit is operating in a single threaded mode;
• responsive to the encounter of the long-latency miss, enter a load lookahead mode in the processing unit;
• responsive to entering the load lookahead mode:
• dispatch each instruction from a first set of instructions from a first buffer with an associated vector, wherein the associated vector is within a set of vectors in a first vector array;
• fetch additional instructions into the first buffer in order until the first buffer is full;
• responsive to filling the first buffer, fetch the additional instructions into a second buffer in order until the second buffer is full;
• and
• responsive to filling the second buffer, stop the fetch of the additional instructions;
• determine whether the first set of instructions from the first buffer have completed execution;
• and
• responsive to completed execution of the first set of instructions from the first buffer:
• copy the set of vectors from the first vector array to a second vector array;
• and
• dispatch a second set of instructions from the second buffer with an associated vector from the second vector array.