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US 8,145,883 B2Granted
Preloading instructions from an instruction set other than a currently executing instruction set
AssigneeQUALCOMM Incorporation
InventorsThomas Andrew Sartorius, Brian Michael Stempel, Rodney Wayne Smith
Life of this patent
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Abstract
A preload instruction in a first instruction set is executed at a processor. The preload instruction causes the processor to preload one or more instructions into an instruction cache. The pre-loaded instructions are pre-decoded according to a second instruction set that is different from the first instruction set. The preloaded instructions are pre-decoded according to the second instruction set in response to an instruction set preload indicator (ISPI).
Claims27
A method of preloading instructions, the method comprising:
- at an instruction execution unit of a processor executing in a first instruction set operating mode associated with a first instruction set of a plurality of instruction sets, generating an instruction set preload indicator identifying a second instruction set of the plurality of instruction sets, wherein the first instruction set includes at least one instruction that is not included in the second instruction set;
- executing, in accordance with the first instruction set operating mode, a preload instruction in the first instruction set operative to preload an instruction into an instruction cache, the preload instruction causing pre-loaded instructions to be pre-decoded according to the second instruction set;
- and
- while executing in accordance with the first instruction set operating mode, pre-decoding the pre-loaded instruction in the instruction cache according to a second instruction set operating mode associated with the identified second instruction set.
1 more element
A processor, comprising:
- a memory interface;
- an instruction cache operative to store instructions and pre-decode information;
- an instruction execution unit operative to retrieve the instructions when the processor is in a first instruction set operating mode and to generate an instruction set preload indicator;
- and
- a pre-decoder, interposed between the instruction cache and the memory interface, operative to pre-decode pre-loaded instructions in the instruction cache according to a second instruction set operating mode in response to the instruction set preload indicator, while the instruction execution unit operates in the first instruction set operating mode, the pre-loaded instructions of the second instruction set preloaded in response to a preload instruction in the first instruction set,
- wherein the first instruction set operating mode is associated with the first instruction set of the processor, wherein the second instruction set operating mode is associated with a second instruction set of the processor, and wherein the first instruction set has a first code density that is different than a second code density of the second instruction set.
3 more elements
A non-transitory computer-readable medium storing one or more instructions in a first instruction set of a plurality of instruction sets, wherein the one or more instructions are executable by a processor to cause the processor to:
- generate an instruction set preload indicator identifying a second instruction set of the plurality of instruction sets, wherein the first instruction set includes at least one instruction that is not included in the second instruction set;
- execute, in accordance with a first instruction set operating mode, the preload instruction in the first instruction set operative to preload an instruction into an instruction cache, the preload instruction causing pre-loaded instructions to be pre-decoded according to the second instruction set;
- and
- while executing in accordance with the first instruction set operating mode, pre-decode the pre-loaded instruction in the instruction cache according to a second instruction set operating mode associated with the identified second instruction set.
1 more element
A processor, comprising:
- a memory interface;
- a means for storing instructions and pre-decoding information in an instruction cache;
- a instruction execution means for retrieving the instructions when a processor is in a first instruction set operating mode and for generating an instruction set preload indicator;
- and
- a means for pre-decoding, interposed between the means for storing instructions and the memory interface, for pre-loading instructions according to a second instruction set operating mode into the means for storing instructions in response to the instruction set preload indicator, while the instruction execution means operates in the first instruction set operating mode, the pre-loaded instructions according to the second instruction set operating mode preloaded in response to a preload instruction in a first instruction set;
- wherein the first instruction set operating mode is associated with the first instruction set of the processor, wherein the second instruction set operating mode is associated with a second instruction set of the processor, and wherein the first instruction set has a first code density that is different than a second code density of the second instruction set.
3 more elements
Dependencies are inferred from the claim text.