Matrix processor data switch routing systems and methods

A method comprising:

• programming a first matrix link-enable register field and a second matrix link-enable register field in a matrix processor of an integrated circuit comprising a microprocessor matrix of mesh-interconnected matrix processors, the matrix processor including a data switch configured to control a routing of inter-processor messages through a plurality of inter-processor matrix links of the matrix processor, the first matrix link-enable register field specifying a first link-enable status for a corresponding link of the plurality of inter-processor matrix links, the second matrix link-enable register field specifying a second link-enable status for the corresponding link, wherein the first link enable status is an enabled or disabled status for the corresponding link for an entire inter-processor message category selected from a group consisting of broadcast messages and processor-to-processor messages, and wherein the first matrix link-enable register field includes at least one bit specifying an enabled or disabled status for the entire inter-processor message category for each for the plurality of inter-processor matrix links;
• and
• employing the data switch to route an inter-processor message through the matrix according to the first matrix link enable register field.

A system comprising:

• means for programming a first matrix link-enable register field and a second matrix link-enable register field in a matrix processor of an integrated circuit comprising a microprocessor matrix of mesh-interconnected matrix processors, the matrix processor including a data switch configured to control a routing of inter-processor messages through a plurality of inter-processor matrix links of the matrix processor, the first matrix link-enable register field specifying a first link-enable status for a corresponding link of the plurality of inter-processor matrix links, the second matrix link-enable register field specifying a second link-enable status for the corresponding link, wherein the first link enable status is an enabled or disabled status for the corresponding link for an entire inter-processor message category selected from a group consisting of broadcast messages and processor-to-processor messages, and wherein the first matrix link-enable register field includes at least one bit specifying an enabled or disabled status for the entire inter-processor message category for each for the plurality of inter-processor matrix links;
• and
• means for routing an inter-processor message through the matrix according to the first matrix link enable register field.