Computer memory architecture for hybrid serial and parallel computing systems

An apparatus comprising:

• a serial processor to execute instructions in a computing program primarily in serial;
• a first, private memory to store data solely for use by the serial processor in executing the instructions;
• a plurality of parallel processors to execute instructions in the computing program primarily in parallel, at least one parallel processor of the plurality of parallel processors having a second, local read-only memory;
• and
• a plurality of shared memory modules to store data for use by the plurality of parallel processors in executing the instructions;
• wherein prior to a transition from a serial processing mode to a parallel processing mode, the serial processor is to broadcast a prefetching signal to the plurality of parallel processors to initiate prefetching of data from at least one of the plurality of shared memory modules.

A method of transitioning between a serial processing mode and a parallel processing mode in a computing system, the method comprising:

• while in the serial processing mode, transferring updated data from a first private serial memory of a serial processor to at least one shared memory module of a plurality of shared memory modules;
• receiving a corresponding acknowledgement from the at least one shared memory module that the updated data has been queued or committed for storage in memory, prior to any memory requests from a parallel processor of a plurality of parallel processors;
• and
• broadcasting a first signal to the plurality of parallel processors for substantially concurrent initiation of the parallel processing mode.