Address generation for quadratic permutation polynomial interleaving

A method for address generation, comprising:

• obtaining a block size and a skip value;
• initializing a plurality of addresses, a plurality of increment values, and a step value, the initializing of the addresses and the increment values being performed as a first loop having a first count index x bounded by the skip value obtained;
• wherein the initializing of the plurality of addresses follows from:
• Π(x)=(f1x+f2x2)mod K,
• where K is the block size, where f1 and f2 are respective coefficients associated with a quadratic formula, and wherein the initializing of the plurality of increment values follows from:
• Π′(x)=[f2(2nx+n2)+f1n)]mod K,
• where the increment value Π′(x) is a derivation of the address Π(x), and where n is the skip value and x is the first count index for incrementally counting from a first initial value to a first terminal value;
• setting, by a processor, a second count index for incrementally counting from a second initial value to a second terminal value for a second loop, the second terminal value being bounded by the block size;
• for the second count index not in excess of the second terminal value, iteratively:
• selecting an output address for output from a phase of a plurality of phases;
• and
• incrementing the second count index;
• updating the selected address of the plurality of addresses as being equal to summation of the selected address and its associated increment modulo the block size;
• and
• updating the increment associated with the selected address as being equal to summation of the increment and the step value modulo the block size;
• and
• outputting a sequence of addresses responsive to iterative generation of the output address.

An apparatus for address generation, comprising:

• first storage having a step value;
• second storage having a block size;
• a first subtractor coupled to the first storage and the second storage to respectively receive the step value and the block size as inputs for subtracting the block size from the step value to output a first difference;
• an increment stage coupled to receive the step value and the first difference;
• the increment stage configured to update a first increment as being equal to summation of the first increment and the step value modulo the block size and output the updated first increment;
• the increment stage further configured to update a second increment as being equal to summation of the second increment and the step value modulo the block size and output the updated second increment;
• a second subtractor coupled to the second storage and the increment stage to respectively receive the block size and the updated first increment as inputs for subtracting the block size from the updated first increment to output a second difference;
• a third subtractor coupled to the second storage and the increment stage to respectively receive the block size and the updated second increment as inputs for subtracting the block size from the updated second increment to output a third difference;
• an address stage coupled to receive the updated first and second increments and the second and third differences;
• the address stage configured to update a first address as being equal to summation of the updated first increment and the first address modulo the block size to output an updated first address;
• the address stage further configured to update a second address as being equal to summation of the updated second increment and the second address modulo the block size to output an updated second address;
• control circuitry configured for initializing the first address, the second address, the first increment, the second increment, and the step value;
• the control circuitry further configured to provide a count index associated with counting iterations from 1 to the block size as associated with a sequence;
• the control circuitry further configured to select one of the updated first or second addresses for output from a value stream of a plurality of value streams;
• the selection of the updated first or second addresses responsive to modulo a skip value of the count index for there being at least two value streams of the plurality of value streams;
• and
• the at least two value streams including a first value stream and a second value stream for respectively selecting the first address or the second address therefrom.