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US 8,145,874 B2Granted
System and method of data forwarding within an execution unit
AssigneeQUALCOMM Incorporated
InventorsSuresh Venkumahanti, Lucian Codrescu, Lin Wang
Life of this patent
Estimating the term…
Abstract
In an embodiment, a method is disclosed that includes, comparing, during a write back stage at an execution unit, a write identifier associated with a result to be written to a register file from execution of a first instruction to a read identifier associated with a second instruction at an execution pipeline within an interleaved multi-threaded (IMT) processor having multiple execution units. When the write identifier matches the read identifier, the method further includes storing the result at a local memory of the execution unit for use by the execution unit in the subsequent read stage.
Claims27
A method comprising:
- during a write back stage at an execution unit of a plurality of execution units, comparing a write identifier associated with a result from an execution of a first instruction to a read identifier associated with a second instruction at an execution pipeline within an interleaved multi-threaded (IMT) processor that includes the plurality of execution units;
- storing the result at a register file;
- and
- storing the result at a local memory of the execution unit in response to determining that the write identifier matches the read identifier, wherein the result stored at the register file is provided from the register file to the execution unit without passing through the local memory.
1 more element
A method comprising:
- determining a second address associated with a second packet of instructions from a first address associated with a first packet of instructions;
- examining a carry bit of an adder of a data unit to determine whether the second address crossed a boundary of a cache line associated with a multi-way cache;
- in response to determining the second address crossed the boundary of the cache line associated with the multi-way cache, examining a second carry bit of the adder of the data unit to determine whether the second address crossed a boundary of a page associated with the multi-way cache;
- and
- in response to determining the boundary of the cache line is not crossed, accessing the multi-way cache to retrieve data from the second address using tag array data and translation look-aside buffer (TLB) lookup data associated with the first address that was determined from a previous tag array lookup operation.
2 more elements
A multi-threaded processor comprising:
- an execution unit comprising:
- a local memory to store one or more data values;
- and
- a logic circuit adapted to determine whether a read address associated with a read operation matches a write back address associated with a previous write back operation, the logic circuit adapted to store the one or more data values at the local memory in response to determining that the read address matches the write back address and the logic circuit adapted to store the one or more data values at a memory external to the execution unit, wherein the logic circuit is further adapted to provide to the execution unit the one or more data values stored at the memory external to the execution unit without the one or more data values stored at the memory external to the execution unit passing through the local memory.
1 more element
A processor comprising:
- means for comparing a write identifier associated with a result to be written to a register file from execution of a first packet of instructions to a read identifier associated with a second packet of instructions at an execution pipeline within an interleaved multi-threaded (IMT) processor having multiple execution units;
- means for writing the result to the register file;
- means for storing the result locally at an execution unit in response to determining that the write identifier matches the read identifier;
- and
- means for providing the result written to the register file to an execution unit to use in connection with execution of the second packet of instructions, wherein the result written to the register file is provided from the register file to the execution unit without passing through the means for storing the result locally.
2 more elements
A non-transitory computer-readable medium including program code that, when executed by a processor, causes the processor to:
- during a write back stage at an execution unit of a plurality of execution units, compare a write identifier associated with a result from an execution of a first instruction to a read identifier associated with a second instruction at an execution pipeline within an interleaved multi-threaded (IMT) processor that includes the plurality of execution units;
- store the result at a register file;
- and
- store the result at a local memory of the execution unit in response to determining that the write identifier matches the read identifier, wherein the result stored at the register file is provided from the register file to the execution unit without passing through the local memory.
1 more element
A non-transitory computer-readable medium including program code that, when executed by a processor, causes the processor to:
- determine a second address associated with a second packet of instructions from a first address associated with a first packet of instructions;
- examine a carry bit of an adder of a data unit to determine whether the second address crossed a boundary of a cache line associated with a multi-way cache;
- in response to determining the second address crossed the boundary of the cache line associated with the multi-way cache, examine a second carry bit of the adder of the data unit to determine whether the second address crossed a boundary of a page associated with the multi-way cache;
- and
- in response to determining the boundary of the cache line is not crossed, access the multi-way cache to retrieve data from the second address using tag array data and translation look-aside buffer (TLB) lookup data associated with the first address that was determined from a previous tag array lookup operation.
2 more elements
Dependencies are inferred from the claim text.