US 8,145,869 B2Granted

Data access and multi-chip controller

AssigneeBroadbus Technologies, Inc.

InventorsMatthew G. Sargeant, Michael A. Kahn, Francis J. Stifter, Jr., Jason P. Colangelo

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Abstract

A single data bus to a memory device can be split up into a number of data bus portions, each of which is managed by a different respective controller chip of multiple controller chips. During a memory access to a respective memory device, each of the multiple controller chips controls a different corresponding portion of the data bus to retrieve data from or store data to the memory device depending on whether the access is a read or write. To perform the data access, a synchronizer circuit (internal and/or external to the memory controller chips) synchronizes the multiple memory controller chips such that one of the memory controller chips drives the address bus and/or control signals to the memory device. After setting the address to the memory device, the memory controller chips either read data from or write data to the memory device based on the address.

Claims12

Dependent claims

A method for controlling multiple data buses including a first data bus to a first memory device and a second data bus to a second memory device, the method comprising:

splitting the first data bus to the first memory device into multiple sets of first data bus signals;
for each of multiple controller chips, assigning a respective controller chip to control a corresponding set of the multiple sets of the first data bus signals associated with the first data bus between the respective controller chip and the first memory device;
splitting the second data bus to the second memory device into multiple sets of second data bus signals;
for each of the multiple controller chips, assigning a respective controller chip to control a corresponding set of the multiple sets of the second data bus signals associated with the second data bus between the respective controller chip and the second memory device;
via the first data bus, enabling each of the multiple chip controllers to simultaneously access a different respective portion of data stored in the first memory device;
via the second data bus, enabling each of the multiple chip controllers to simultaneously access a different respective portion of data stored in the second memory device;
and
synchronizing the multiple chip controllers for purposes of enabling simultaneous access of different portions of data from the first memory device at the same time and enabling simultaneous access of different portions of data from the second memory device at the same time;
wherein enabling each of the multiple chip controllers to simultaneously access the different respective portions of data stored in the first memory device includes:
assigning a first controller chip of the multiple controller chips to control a first address bus and first control bus associated with the first memory device;
and
wherein enabling each of the multiple chip controllers to simultaneously access the different respective portions of data stored in the second memory device includes:
assigning a second controller chip of the multiple controller chips to control a second address bus and second control bus associated with the second memory device,
enabling the first and second controller chips to simultaneously access a respective portion of data from the first memory device while the first controller chip controls the first address bus and first control bus associated with the first memory device;
and
enabling the first and second controller chips to simultaneously access a respective portion of data from the second memory device while the second controller chip controls the second address bus and second control bus associated with the second memory device.

13 more elements

A system comprising:

a first data bus split up into multiple sets of first data bus signals;
multiple memory controller chips, each of which is assigned to control a corresponding set of the multiple sets of first data bus signals to a first memory device;
and
the first data bus enabling each of the multiple chip controllers to simultaneously access a different respective portion of data stored in the first memory device,
a second data bus split up into multiple sets of second data bus signals, each of the multiple memory controller chips being assigned to control a corresponding set of the multiple sets of second data bus signals to a second memory device;
and
a synchronization circuit to coordinate operations associated with the multiple memory controller chips, wherein signaling associated with the synchronization circuit enables the multiple chip controllers to simultaneously access a different respective portion of data stored in the second memory device via the second data bus;
wherein a first controller chip of the multiple controller chips is configured to control a first address bus and corresponding first control bus associated with the first memory device;
and
wherein a second controller chip of the multiple controller chips is configured to control a second address bus and corresponding second control bus associated with the second memory device.

7 more elements

Dependencies are inferred from the claim text.