Non-volatile memory devices for outputting data using double data rate (DDR) operations and methods of operating the same
AssigneeSamsung Electronics Co., Ltd.
InventorDong-ryul Ryu
Life of this patent
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Abstract
A non-volatile memory device is operated by outputting data in response to an alternating sequence of first and second edges of a read control signal, respectively. A determination is made whether the read control signal and a write control signal are in synchronization at one of the first edges. Output of the data is stopped at the second edge that follows the one of the first edges of the read control signal if the read control signal and the write control signal are in synchronization at the one of the first edges.
Claims23
A method of operating a non-volatile memory device, comprising:
- outputting data in response to an alternating sequence of first and second edges of a read control signal, respectively;
- determining whether the read control signal and a write control signal are in synchronization at one of the first edges;
- and
- stopping an output of the data at the second edge that follows the one of the first edges of the read control signal responsive to the read control signal and the write control signal being in synchronization at the one of the first edges.
A non-volatile memory device, comprising:
- a page buffer that is configured to store a portion of data stored in a non-volatile memory array;
- a selector that is configured to output data stored in the page buffer corresponding to an address value of an address signal;
- an output unit that is configured to be activated and deactivated responsive to an enable signal and a disable signal, respectively, and is further configured to output data from the selector through an input/output pin;
- an address signal generator that is configured to decode an initial address, generate the address signal, and change an address value of the address signal responsive to a sub read control signal;
- and
- a data read controller that is configured to generate the sub read control signal with a frequency double that of the read control signal responsive to the read control signal, and to generate the disable signal responsive to a write control signal.
A method of operating a non-volatile memory device, comprising:
- counting first edges of a flash clock signal that comprises an alternating sequence of first and second edges responsive to a read recognition signal;
- outputting data responsive to the first and second edges of the flash clock signal from a time beginning at the (n+1)-th first edge of the flash clock signal if a count of the first edges of the flash clock signal reaches n;
- and
- stopping an output of the data if a count of the output data reaches m.
A non-volatile memory device, comprising:
- a page buffer that is configured to store a portion of data stored in a non-volatile memory array;
- a selector that is configured to output data stored in the page buffer corresponding to an address value of an address signal;
- an output unit that is configured to be activated and deactivated responsive to an enable signal and a disable signal, respectively, and is further configured to output data from the selector through an input/output pin;
- a first counter that is configured to generate the disable signal if a count of the output data reaches m;
- an address signal generator that is configured to decode an initial address, generate the address signal, and change an address value of the address signal responsive to a sub flash clock signal;
- and
- a data read controller that is configured to generate the sub flash clock signal with a frequency double that of the flash clock if a count of first edges of the flash clock signal is n.
Dependencies are inferred from the claim text.