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US 8,145,866 B2Granted
Selective register reset
AssigneeMicron Technology, Inc.
InventorJune Lee
Life of this patent
Estimating the term…
Abstract
The present disclosure includes methods, devices, modules, and systems for storing selective register reset. One method embodiment includes receiving an indication of a die and a plane associated with at least one address cycle. Such a method can also include selectively resetting a particular register of a number of registers, the particular register corresponding to the plane and the die.
Claims25
A method for operating a memory device, comprising:
- receiving an indication of a die and a plane associated with at least one address cycle;
- and
- selectively resetting a particular register of a number of registers, the particular register corresponding to the plane and the die.
A method for an interleaving operation of a memory device, comprising in order:
- loading at least a partial first page of data from a first plane to at least one section of a first register;
- selectively resetting at least one section of a second register;
- loading at least a partial second page of data from I/O circuitry to the at least one section of the second register;
- and
- reading at least the partial first page of data from the at least one section of the first register.
2 more elements
A method for operating a memory device, comprising:
- receiving a starting address associated with at least one address cycle, wherein the starting address corresponds to a particular section of the register;
- and
- selectively resetting the particular section of the register.
A memory device, comprising:
- a first plane of memory cells associated with a first register;
- a second plane of memory cells associated with a second register;
- and
- control circuitry coupled to the first and the second planes and configured to selectively send a reset signal to the first register without sending a reset signal to the second register.
1 more element
A memory device, comprising:
- one or more planes of memory cells associated with one or more registers;
- the one or more registers divided into two or more sections;
- and
- control circuitry coupled to the one or more planes and configured to selectively send reset signals to at least one of the one or more registers on a section-by-section basis.
1 more element
Dependencies are inferred from the claim text.