Interleave control device, interleave control method, and memory system
AssigneeKabushiki Kaisha Toshiba
InventorTadaaki Kinoshita
Life of this patent
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Abstract
According to one embodiment, an interleave control device of a memory system includes a memory divided into sections, and a data bus used, in common, for data transfers for the sections, the device comprises a detector and a start module. The detector is configured to detect a transfer of data of a predetermined size during a transfer of data on the data bus to be written to a certain section of the memory or data read from the section. The start module is configured to start a transfer of interleave control data in place of the data to be written or the read data when the detector detects the transfer of the data of the predetermined size.
Claims13
An interleave control device of a memory system comprising a memory comprising sections, and a data bus for data transfers between the sections, the device comprising:
- a detector configured to detect a completion of transfer of data of a predetermined size during a transfer of data on the data bus to be written to a section of the memory or data read from the section;
- and
- a start module configured to start a transfer of interleave control data in place of the data to be written or the read data when the detector detects the completion of transfer of the data of the predetermined size.
An interleave control method of a memory system comprising a memory comprising sections, and a data bus for data transfers between the sections, the method comprising:
- detecting a completion of transfer of data of a predetermined size during a transfer of data on the data bus to be written to a section of the memory or data read from the section;
- and
- starting a transfer of interleave control data in place of the data to be written or the read data when the completion of transfer of the data of the predetermined size is detected.
A memory system connectable to a host system, comprising:
- nonvolatile semiconductor memories;
- a data bus connected to the nonvolatile semiconductor memories;
- and
- a memory controller connected to the host system, further connected to the nonvolatile semiconductor memories, and configured to control data transfer on the data bus, wherein the memory controller comprises:
- a detector configured to detect a completion of transfer of data of a predetermined size during a transfer of data on the data bus to be written to a section of the memory or data read from the section;
- and
- a start module configured to start a transfer of interleave control data in place of the data to be written or the read data when the detector detects the completion of transfer of the data of the predetermined size.
Dependencies are inferred from the claim text.