# US 8,140,738 B2 · Flash memory interface device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,140,738 B2 - Document ID: US8140738B2 - Status: Granted - Kind: B2 - Application number: 11/780,441 - Filed: 2007-07-19 - Published: 2008-02-28 - Granted: 2012-03-20 - Earliest claimed: 2006-07-20 - Assignees: STMicroelectronics Pvt. Ltd. - Inventors: Deboleena Minz; Sanjeev Varshney - Web page: https://patentgrep.com/patent/US8140738B2 ## CPC - G06F 13/1694: {Configuration of memory controller to different memory types} - G11C 16/32: Timing circuits - G11C 2216/30: Reduction of number of input/output pins by using a serial interface to transmit or receive addresses or data, i.e. serial access memory - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A memory interface module provides interfacing between a host processor with multiple flash memories and parallel interfaces of varying protocols. The interface module includes multiple register files, multiple operation information registers, an internal memory, a flash interface portion, and a finite state machine (FSM). The register files receive a command from the host processor for controlling an operation of multiple flash memories. The operation information registers execute and store the command and operation information. The internal memory receives and stores host data from the host processor. The internal memory further stores flash data extracted from multiple flash memories. The flash interface portion interacts with the memory devices connected to the controller. The FSM extracts the command and the operation information from the register files, which are programmed by the user and controls the control signals of the memory devices connected to the controller through the flash interface. ## Claims ### Claim 1 A memory interface module for interfacing between a host processor and a plurality of flash memories, the plurality of flash memories obeying a plurality of different protocols, said memory interface module comprising: a flash interface configured to be coupled between a host processor connection to the memory interface module and each of the plurality of flash memories, the flash interface supplying driving device control signals; a plurality of register files including: an address register configured to store an address of a memory read/write location in a particular one of the plurality of flash memories and a command register configured to store device commands to control operation of that particular one of the plurality of flash memories; a plurality of operation information registers configured to store a command received from the host processor to control flash memory operation; a finite state machine (FSM) configured to extract the command from the operation information registers, the FSM including a plurality of states relating to driving device control signals with respect to each of the plurality of flash memories, there being a sequence of states for interfacing with each of the plurality of flash memories, wherein transitions between the plurality of states in the sequence of states are controlled by software in the form of instruction-operand pairs executed in response to the extracted command, each instruction-operand pair controlling the generation of the device control signals supplied by the flash interface, wherein the operand of certain instruction-operand pairs identifies the address register within the register files which stores the memory read/write location address, and wherein the operand of certain other instruction-operand pairs identifies the command register within the register files which stores the device command. ### Claim 2 (depends on 1) The memory interface module of claim 1 wherein the plurality of register files further includes a timing register configured to store timing information for accessing that particular one of the plurality of flash memories, and wherein the operand of other instruction-operand pairs identifies the timing register within the register files which stores the timing information. ### Claim 3 (depends on 1) The memory interface module of claim 1, wherein the plurality of flash memories is selected from a group consisting of flash memories, SDRAMs, and parallel interfaces. ### Claim 4 (depends on 1) The memory interface module of claim 1, wherein the flash interface includes a plurality of input/output pins connected through a glue logic to the plurality of flash memories; and wherein the transitions between the plurality of states in the sequence of states of the FSM supplies the driving device control signals on the plurality of input/output pins in accordance with the plurality of different protocols for memory access so as to interface with the plurality of flash memories. ### Claim 5 (depends on 4) The memory interface module of claim 4 wherein the plurality of input/output pins includes a first input/output pin connected through the glue logic to both a first type flash memory and a second type flash memory, the FSM configured to control the first input/output pin to operate in a first mode for interfacing with the first type flash memory in accordance with its protocol for memory access and a second mode for interfacing with the second type flash memory in accordance with its protocol for memory access. ### Claim 6 (depends on 4) The memory interface module of claim 4 wherein the plurality of flash memories comprise a first type flash memory and a second type flash memory, and wherein the first type flash memory utilizes a first protocol for memory access and the second type flash memory utilizes a second protocol for memory access, the FSM configured to control the first input/output pin to operate in accordance with the first protocol for memory access for interfacing with the first type flash memory and in accordance with the second protocol for memory access for interfacing with the second type flash memory. ### Claim 7 (depends on 1) The memory interface module of claim 1 wherein the plurality of flash memories comprise a first type flash memory and a second type flash memory, and wherein the first type flash memory utilizes a first control signal sequence in accordance with its protocol for memory access and the second type flash memory utilizes a second control signal sequence in accordance with its protocol for memory access, the transitions between the plurality of states in the sequence of states implemented by the FSM causing the flash interface to effectuate the first control signal sequence when interfacing with the first type flash memory and effectuate the second control signal sequence when interfacing with the second type flash memory. ### Claim 8 (depends on 1) The memory interface module of claim 1 wherein the plurality of memories comprise a first type flash memory and a second type flash memory, and wherein a first sequence of states implemented by the FSM is used to access the first type flash memory in accordance with a first protocol for memory access and a second sequence of states implemented by the FSM is used to access the second type flash memory in accordance with a second protocol for memory access. ### Claim 9 (depends on 1) The memory interface module of claim 1 wherein the instruction-operand pairs include a repeat instruction-operand pair which, when executed by the FSM, repeats a state relating to a driving device control signal with respect to one of the plurality of flash memories. ### Claim 10 (depends on 9) The memory interface module of claim 9 further including an internal memory buffer configured to store data in response to repeated execution by the FSM in accordance with the repeat instruction-operand pair. ### Claim 11 A memory interface module for interfacing between a host processor and a plurality of flash memories, the plurality of flash memories obeying a plurality of different protocols, said memory interface module comprising: a flash interface configured to be coupled between a host processor connection to the memory interface module and each of the plurality of flash memories, the flash interface supplying driving device control signals; a first plurality of register files including: a first address register configured to store an address of a memory read/write location in a first one of the plurality of flash memories and a first command register configured to store device commands to control operation of that first one of the plurality of flash memories; a second plurality of register files including: a second address register configured to store an address of a memory read/write location in a second one of the plurality of flash memories and a second command register configured to store device commands to control operation of that second one of the plurality of flash memories; a plurality of operation information registers configured to store a command received from the host processor to control flash memory operation; a finite state machine (FSM) configured to extract the command from the operation information registers, the FSM including a plurality of states relating to driving device control signals with respect to each of the plurality of flash memories, there being a sequence of states for interfacing with each of the plurality of flash memories, wherein transitions between the plurality of states in the sequence of states are controlled by software in the form of instruction-operand pairs executed in response to the extracted command, each instruction-operand pair controlling the generation of the device control signals supplied by the flash interface, wherein the operand of certain instruction-operand pairs identifies the address register within the register files which stores the memory read/write location address, and wherein the operand of certain other instruction-operand pairs identifies the command register within the register files which stores the device command; and wherein one of the first and second register files is configured to be programmed with address and device commands while the address and device commands stored in the other of the first and second register files are being accessed by the finite state machine in connection with driving device control signals.