Buffering unit to support graphics processing operations
AssigneeNVIDIA Corporation
InventorsAndrew J. Tao, Vimal S. Parikh, Yan Yan Tang
Life of this patent
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Abstract
An apparatus and method for buffering graphics data are described. In one embodiment, a graphics processing apparatus includes a storage unit and a reorder control unit that is connected to the storage unit. The reorder control unit is configured to coordinate storage of vertex attributes in the storage unit so as to convert the vertex attributes from an initial order to a modified order. The reorder control unit is configured to identify a subset of the vertex attributes to be stored within a common range of addresses in the storage unit, and the reorder control unit is configured to access the storage unit such that the subset of the vertex attributes is written into the storage unit substantially in parallel.
Claims7
A graphics processing apparatus, comprising:
- a storage unit;
- and
- a reorder control unit connected to the storage unit, the reorder control unit configured to coordinate storage in the storage unit so as to convert from an initial order to a modified order, the reorder control unit configured to group vertex attributes of different types for a common vertex into at least a first group and a second group, the reorder control unit configured to identify the first group to be stored within a first common range of addresses in the storage unit, the reorder control unit configured to identify the second group to be stored within a second common range of addresses in the storage unit, the reorder control unit configured to access the storage unit such that the first group is written into the storage unit substantially in parallel, the reorder control unit configured to access the storage unit such that the second group is written into the storage unit substantially in parallel and subsequent to writing the first group into the storage unit,
- wherein the storage unit is configured with multiple partitions including respective ranges of addresses.
A graphics processing method, comprising:
- receiving vertex attributes of different types for a common vertex, the vertex attributes having an initial order;
- mapping the vertex attributes onto addresses in a storage unit so as to covert the vertex attributes to a modified order;
- identifying a first subset of the vertex attributes that is mapped onto a first range of addresses in the storage unit;
- issuing a first write request to the storage unit such that the first subset of the vertex attributes is written into the first range of addresses substantially in parallel;
- identifying a second subset of the vertex attributes that is mapped onto a second range of addresses in the storage unit;
- and
- issuing a second write request to the storage unit such that the second subset of the vertex attributes is written into the second range of addresses substantially in parallel.
Dependencies are inferred from the claim text.