Floating point execution unit for calculating a one minus dot product value in a single pass
AssigneeInternational Business Machines Corporation
InventorsAdam James Muff, Matthew Ray Tubbs
Life of this patent
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Abstract
A floating point execution unit calculates a one minus dot product value in a single pass. As such, the dependency that otherwise would be required to perform the calculations is eliminated, resulting in a substantially faster performance of such calculations. The floating point execution unit may be used, for example, to accelerate pixel shading algorithms such as Fresnel and electron microscope effects.
Claims22
A method of applying a shading effect to a pixel in an image using a vector floating point execution unit, the method comprising:
- receiving a one minus dot product instruction defined in an instruction set supported by the processing unit, the one minus dot product instruction configured to receive a surface normal vector and a view vector, each of the surface normal and view vectors including x, y and z values;
- and
- calculating an intensity value from the surface normal vector and the view vector by executing the one minus dot product instruction in a single pass through a plurality of stages of a multi-stage pipeline of the vector floating point execution unit, wherein executing the one minus dot product instruction includes:
- multiplying the respective x, y and z values from the surface normal and view vectors in respective first, second and third processing lanes of the multi-stage pipeline of the vector floating point execution unit;
- negating each of the first, second and third processing lanes of the vector floating point execution unit;
- forcing a fourth processing lane of the multi-stage pipeline of the vector floating point execution unit to a 1.0 value;
- and
- summing the first, second, third and fourth processing lanes to generate the intensity value.
A circuit arrangement, comprising a vector floating point execution unit including a pipeline with a plurality of stages and configured to execute a first instruction of a first instruction type from an instruction set to calculate a one minus dot product value in a single pass through the plurality of stages of the pipeline of the vector floating point execution unit, wherein the pipeline of the vector floating point execution unit includes:
- a plurality of processing lanes, each processing lane including multiplication logic configured to generate a product;
- and
- addition logic in communication with the plurality of processing lanes and configured to sum respective outputs of the plurality of processing lanes;
- wherein the vector floating point execution unit is configured to, in response to the first instruction, and in the single pass through the plurality of stages of the pipeline, use the multiplication logic in multiple processing lanes among the plurality of processing lanes to calculate a plurality of products for the one minus dot product value, and use the addition logic to sum the plurality of products with a constant value.
A method of performing a one minus dot product calculation using a vector floating point execution unit, the method comprising:
- receiving a first instruction of a first instruction type from an instruction set supported by the vector floating point execution unit;
- and
- in response to receiving the first instruction, executing the first instruction by calculating a one minus dot product value in a single pass through a plurality of stages of a pipeline of the vector floating point execution unit, wherein the pipeline of the vector floating point execution unit includes a plurality of processing lanes, each processing lane including multiplication logic configured to generate a product, and addition logic in communication with the plurality of processing lanes and configured to sum respective outputs of the plurality of processing lanes, wherein executing the first instruction includes, in the single pass through the plurality of stages of the pipeline:
- using the multiplication logic in multiple processing lanes among the plurality of processing lanes to calculate a plurality of products for the one minus dot product value;
- and
- using the addition logic to sum the plurality of products with a constant value.
Dependencies are inferred from the claim text.