PLL frequency synthesizer

A frequency synthesizer comprising:

• a voltage-controlled oscillator which oscillates signals at a frequency according to a control voltage;
• a frequency divider which divides the frequency of an output signal of voltage-controlled oscillator and for which a frequency division ratio is variably-set at a ratio selected from among a plurality of frequency division ratios in response to a frequency selection signal;
• a phase frequency detector which compares a phase of a reference input signal having a standard frequency with a phase of a frequency-divided output signal of the frequency divider and outputs a phase difference signal;
• a control voltage generation unit which generates the control voltage according to the phase difference signal;
• a frequency range tuning circuit which detects a frequency control code that sets a voltage-controlled frequency range of the voltage-controlled oscillator corresponding to the frequency division ratio which is variably-set;
• and
• a frequency control code memory which stores the frequency control code detected by the frequency range tuning circuit corresponding to the frequency division ratio;
• and
• wherein in an initialization interval, the frequency range tuning circuit detects a plurality of frequency control codes which are detected;
• and
• in a normal operation interval, one of the plurality of frequency control codes is output to the voltage-controlled oscillator selectively in response to the frequency selection signal;
• wherein a first frequency control code among the plurality of frequency control codes is changed to a second frequency control code among the plurality of frequency control codes without the initialization interval.

A frequency synthesizer comprising:

• a voltage-controlled oscillator which oscillates signals at a frequency according to a control voltage;
• a frequency divider which divides the frequency of an output signal of the voltage-controlled oscillator and for which a frequency division ratio is variably-set at a ratio selected from among a plurality of frequency division ratios in response to a frequency selection signal;
• a phase frequency detector which compares a phase of a reference input signal having a standard frequency with a phase of a frequency-divided output signal of the frequency divider and outputs a phase difference signal;
• a control voltage generation unit which generates the control voltage according to the phase difference signal;
• a frequency range tuning circuit which detects a frequency control code that sets a voltage-controlled frequency range of the voltage-controlled oscillator corresponding to the frequency division ratio which is variably-set;
• and
• a frequency control code memory which stores the frequency control code detected by the frequency range tuning circuit corresponding to the frequency division ratio;
• and
• a selector to select one of the plurality of frequency control codes in response to the frequency selection signal;
• wherein in an initialization interval, the frequency range tuning circuit detects a plurality of frequency control codes which corresponds to the plurality of frequency division ratios respectively, and the frequency control code memory stores the plurality of frequency control codes which are detected;
• and
• in a normal operation interval, one of the plurality of frequency control codes is output to the voltage-controlled oscillator selectively is response to the frequency selection signal.