Device for generating clock in semiconductor integrated circuit

A device for generating a clock in a semiconductor integrated circuit, the device comprising:

• a multi-phase clock generator configured to generate a multi-phase internal clock;
• a first edge combining unit configured to generate a first output clock having a first frequency by combining rising edges of clocks included in the internal clock, and transmit the first output clock to a first port;
• and
• a second edge combing unit configured to generate a second output clock having a second frequency by combining rising edges of clocks included in the internal clock, and transmit the second output clock to a second port,
• wherein the second edge combining unit is configured to extract a predetermined number of clocks, which is defined in accordance with a frequency mode, among the clocks included in the internal clock, and generate the second output clock by combining the rising edges of the extracted clocks.

A device for generating a clock in a semiconductor integrated circuit, the device comprising:

• a rising pulse extracting unit configured to generate a plurality of rising pulse extraction signals toggled to a predetermined level at the rising edges of a portion of pre-assigned clocks among clocks included in a multi-phase internal clock;
• a falling pulse extracting unit configured to generate a plurality of falling pulse extraction signals toggled to a low level at the rising edge of a portion of pre-assigned clocks among clocks included in the multi-phase internal clock;
• a MUX unit configured to generate a plurality of rising pulse signals and a plurality of falling pulse signals by combining the plurality of rising pulse extraction signals and the plurality of falling pulse extraction signals;
• and
• a clock generating unit configured to generate an output clock in response to the plurality of rising pulse signals and the plurality of falling pulse signals.