Symmetric phase detector

A method comprising:

• receiving at a first circuit input a first input signal having a first phase, the first circuit input being connected to a first mixer cell input of a first mixer cell and to a third mixer cell input of a second mixer cell, the first mixer cell having a first mixer cell output, the second mixer cell having a second mixer cell output;
• receiving at a second circuit input a second input signal having a second phase, the second circuit input being connected to a second mixer cell input of the first mixer cell and to a fourth mixer cell input of the second mixer cell;
• producing at the first mixer cell a first delay between the first mixer cell input and the first mixer cell output and a second delay between the second mixer cell input and the first mixer cell output, there being a first difference between the first delay and the second delay;
• and
• producing at the second mixer cell a third delay between the third mixer cell input and the second mixer cell output, and a fourth delay between the fourth mixer cell input and the second mixer cell output, there being a second difference between the third delay and the fourth delay;
• producing at a current mirror a mirrored current of a first-mixer-cell output signal and a mirrored current of a second-mixer-cell output signal;
• and
• combining the first mixer cell output and the second mixer cell output with each other to provide a circuit output signal at a circuit output by adding the mirrored current of the first-mixer-cell output signal and the mirrored current of the second-mixer-cell output signal to produce the circuit output signal, a current of the circuit output signal being proportional to a phase offset between the first phase and the second phase.

A system comprising:

• means for receiving at a first circuit input a first input signal having a first phase, the first circuit input being connected to a first mixer cell input of a first mixer cell and to a third mixer cell input of a second mixer cell, the first mixer cell having a first mixer cell output, the second mixer cell having a second mixer cell output;
• means for receiving at a second circuit input a second input signal having a second phase, the second circuit input being connected to a second mixer cell input of the first mixer cell and to a fourth mixer cell input of the second mixer cell;
• means for producing at the first mixer cell a first delay between the first mixer cell input and the first mixer cell output and a second delay between the second mixer cell input and the first mixer cell output, there being a first difference between the first delay and the second delay;
• and
• means for producing at the second mixer cell a third delay between the third mixer cell input and the second mixer cell output, and a fourth delay between the fourth mixer cell input and the second mixer cell output, there being a second difference between the third delay and the fourth delay;
• means for producing at a current mirror a mirrored current of a first-mixer-cell output signal and a mirrored current of a second-mixer-cell output signal;
• and
• means for combining the first mixer cell output and the second mixer cell output with each other to provide a circuit output signal at a circuit output by adding the mirrored current of the first-mixer-cell output signal and the mirrored current of the second-mixer-cell output signal to produce the circuit output signal, a current of the circuit output signal being proportional to a phase offset between the first phase and the second phase.