Stressed transistors with reduced leakage

Abstract

Integrated circuits with stressed transistors are provided. Stressing transistors may increase transistor threshold voltage without the need to increase channel doping. Stressing transistors may reduce total leakage currents. It may be desirable to compressively stress N-channel metal-oxide-semiconductor (NMOS) transistors and tensilely stress P-channel metal-oxide-semiconductor (PMOS) transistors to reduce leakage currents. Techniques that can be used to alter the amount of stressed experienced by transistors may include forming a stress-inducing layer, forming a stress liner, forming diffusion active regions using silicon germanium, silicon carbon, or standard silicon, implementing transistors in single-finger instead of multi-finger configurations, and implanting particles. Any combination of these techniques may be used to provide appropriate amounts of stress to increase the performance or decrease the total leakage current of a transistor.

Dependencies are inferred from the claim text.