Latency measurements for wireless communications
AssigneeLattice Semiconductor Corporation
InventorsJames Doubler, Michael Hammer, Jin Zhang
Life of this patent
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Abstract
In one embodiment, a programmable logic device (PLD) includes a programmable fabric and hard logic coupled to the programmable fabric. The hard logic includes a timing measurement circuit adapted to measure latency of a data path between first and second points in the programmable logic device, such as the latency of a data path through a link interface configured within the programmable fabric.
Claims19
A programmable logic device comprising:
- a programmable fabric within the device;
- and
- hard logic within the device coupled to the programmable fabric, the hard logic including a timing measurement circuit adapted to measure latency of a data path between first and second points in the programmable logic device.
A programmable logic device comprising:
- a programmable fabric within the device;
- and
- hard logic within the device coupled to the programmable fabric, the hard logic including a timing measurement circuit adapted to measure latency of a data path between multiple points in the programmable logic device, the timing measurement circuit including:
- a plurality of pattern matching circuits, each coupled to one of the points in the device;
- a counter;
- a first multiplexer coupled between at least two pattern matching circuits and the counter;
- a status register coupled to the counter;
- and
- a second multiplexer coupled between at least two pattern matching circuits and the status register.
A non-transitory computer-readable medium on which is stored a computer program for implementing a link interface within a programmable fabric of a programmable logic device, the device including hard logic that implements a timing measurement circuit adapted to measure latency of a data path through the interface from a first point in the device to a second point in the device.
Dependencies are inferred from the claim text.