Apparatus and methods for adjusting performance of integrated circuits
AssigneeAltera Corporation
InventorsDavid Lewis, Vaughn Betz, Irfan Rahim, Peter McElheny, Yow-Juang W. Liu, Bruce Pedersen
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Abstract
A programmable logic device (PLD) includes a delay circuit and a body-bias generator. The delay circuit has a delay configured to represent a delay of user circuit implement in the PLD. The body-bias generator is configured to adjust the body bias of a transistor within the user circuit. The body-bias generator adjusts the body bias of the transistor in response to a level derived from the signal propagation delay of the delay circuit.
Claims12
A programmable logic device (PLD), comprising:
- a plurality of user circuits, each of the user circuits implemented in the programmable logic device (PLD);
- and
- a plurality of body-bias generators, wherein at least one body-bias generator in the plurality of body-bias generators is configured to selectively adjust a body bias of a transistor within at least one user circuit in the plurality of user circuits based in part on a temperature level of the programmable logic device (PLD).
A method of implementing electronic circuits in a programmable logic circuit (PLD), the method comprising:
- implementing a plurality of user circuits in the programmable logic device (PLD);
- and
- using at least one body-bias generator in a plurality of body-bias generators to selectively adjust a body bias of a transistor within at least one user circuit in the plurality of user circuits based in part on a temperature level of the programmable logic device (PLD).
Dependencies are inferred from the claim text.