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US 8,138,593 B2Granted
Packaged microchip with spacer for mitigating electrical leakage between components
AssigneeAnalog Devices, Inc.
InventorsAngelo Pagkaliwangan, Garry Griffin
Life of this patent
Estimating the term…
Abstract
A packaged microchip has a base, at least one spacer coupled to the base, and first and second microchips mounted to the at least one spacer. The at least one spacer is configured to substantially prevent leakage current between the first and second microchips.
Claims24
A packaged microchip comprising:
- a base;
- at least one spacer coupled to the base, the spacer having a substantially uniform thickness;
- and
- first and second microchips mounted to the at least one spacer, the spacer being configured to substantially prevent leakage current between the first and second microchips;
- wherein the spacer is an insulation layer that electrically isolates the first and second microchips from the base;
- wherein the base comprises one of a premolded leadframe package or a postmolded leadframe package
- wherein a first spacer couples with the first microchip and a second spacer couples with the second microchip.
4 more elements
A packaged microchip comprising:
- a base;
- at least one spacer coupled to the base, the spacer having a substantially uniform thickness;
- first and second microchips mounted to the at least one spacer, the spacer being configured to substantially prevent leakage current between the first and second microchips;
- wherein the spacer is an insulation layer that electrically isolates the first and second microchips from the base;
- wherein the base comprises one of a premolded leadframe package or a postmolded leadframe package;
- and
- a first electrical interface and a second electrical interface, the first electrical interface being directly electrically connected with the first microchip, the second electrical interface being directly electrically connected with the second microchip, the first microchip being directly electrically connect with the second microchip, the second microchip electrically isolating the first interface from the second interface.
4 more elements
A packaged microchip comprising:
- a base;
- at least one spacer coupled to the base, the spacer having a substantially uniform thickness;
- and
- first and second microchips mounted to the at least one spacer, the spacer being configured to substantially prevent leakage current between the first and second microchips;
- wherein the spacer is an insulation layer that electrically isolates the first and second microchips from the base;
- wherein the base comprises one of a premolded leadframe package or a postmolded leadframe package
- wherein the at least one spacer comprises a dielectric having a thickness of less than about 0.003 inches.
4 more elements
A packaged microchip comprising:
- a base;
- at least one spacer coupled to the base, the spacer having a substantially uniform thickness;
- and
- first and second microchips mounted to the at least one spacer, the spacer being configured to substantially prevent leakage current between the first and second microchips;
- wherein the spacer is an insulation layer that electrically isolates the first and second microchips from the base;
- wherein the base comprises one of a premolded leadframe package or a postmolded leadframe package
- wherein the at least one spacer has a dielectric strength of between about 3 KV/thousandths of an inch to 6 KV/thousandths of an inch.
4 more elements
A packaged microchip comprising:
- a base;
- at least one spacer coupled to the base, the spacer having a substantially uniform thickness;
- first and second microchips mounted to the at least one spacer, the spacer being configured to substantially prevent leakage current between the first and second microchips;
- wherein the spacer is an insulation layer that electrically isolates the first and second microchips from the base;
- wherein the base comprises a die attach paddle, the at least one spacer being coupled with the die attach paddle;
- and
- a first electrical interface and a second electrical interface, the first electrical interface being directly electrically connected with the first microchip, the second electrical interface being directly electrically connected with the second microchip, the first microchip being directly electrically connect with the second microchip, the second microchip electrically isolating the first interface from the second interface.
4 more elements
A method for constructing a packaged microchip, the method comprising:
- attaching at least one spacer to one or more paddles of a lead frame;
- attaching at least a first and second microchips to the at least one spacer;
- electrically connecting the first and second microchips using wire bonds;
- and
- electrically connecting the first microchip to a first lead and the second microchip to a second lead, wherein the at least one spacer comprises a dielectric having a thickness of less than about 0.003 inches.
2 more elements
A method for constructing a packaged microchip, the method comprising:
- attaching at least one spacer to a lead frame having at least first and second leads;
- attaching at least a first and second microchip to the at least one spacer;
- electrically connecting the first and second microchips using wire bonds;
- and
- electrically connecting the first microchip to the first lead and the second microchip to the second lead, wherein the at least one spacer comprises a dielectric having a thickness of less than about 0.003 inches.
2 more elements
Dependencies are inferred from the claim text.