US 8,138,547 B2Granted

MOSFET on silicon-on-insulator REDX with asymmetric source-drain contacts

AssigneeInternational Business Machines Corporation

InventorsDechao Guo, Shu-Jen Han, Chung-Hsun Lin, Ning Su

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Abstract

A semiconductor device is disclosed that includes a silicon-on-insulator substrate including a buried insulator layer and an overlying semiconductor layer. Source extension and drain extension regions are formed in the semiconductor layer. A deep drain region and a deep source region are formed in the semiconductor layer. A first metal-semiconductor alloy contact layer is formed using tilted metal formation at an angle tilted towards the source extension region, such that the source extension region has a metal-semiconductor alloy contact that abuts the substrate from the source side, as a Schottky contact therebetween and the gate shields metal deposition from abutting the deep drain region. A second metal-semiconductor alloy contact is formed located on the first metal-semiconductor layer on each of the source extension region and drain extension region.

Claims12

Dependent claims

A method for fabricating a semiconductor device, the method comprising:

providing a silicon-on-insulator (SOI) substrate including a buried insulator layer;
forming a semiconductor layer overlying the SOI substrate, the semiconductor layer being doped with a dopant of a first conductivity type;
forming a gate located on the semiconductor layer, the gate including a gate dielectric layer located on the semiconductor layer and a gate conductor layer located on the gate dielectric layer;
forming a source extension region and a drain extension region in the semiconductor layer, the source extension region and the drain extension region contacting the gate dielectric layer, the source extension region and the drain extension region being doped with a dopant of a second conductivity type, which is opposite the first conductivity type;
forming a deep drain region in the semiconductor layer, the deep drain region contacting the drain extension region and abutting the buried insulator layer;
forming a deep source region in the semiconductor layer, the deep source region contacting the source extension region and abutting the buried insulator layer, the deep drain region and the deep source region being doped with a dopant of the second conductivity type;
forming a first metal-semiconductor alloy contact layer using tilted metal formation at an angle tilted towards the source extension region such that the source extension region has a metal-semiconductor alloy contact that abuts the substrate with the first conductive type from the source extension region as a Schottky contact therebetween and the gate shields metal deposition from abutting the deep drain region, wherein the forming the first metal-semiconductor alloy contact layer using tilted metal formation is formed is at the angle θ tilted towards the source extension region such that a size of the angle θ is:
7
⁢
°
<
θ
<
arctan
⁡
(
L
-
2
×
L
1
-
L
g
h
)
where L is a length between gates, L1 is a width of a first spacer surrounding each side of the gates, Lg is a length of the gates;
and h is a height of the gates;
and
forming a second metal-semiconductor alloy contact located on the first metal-semiconductor layer on each of the source extension region and drain extension region.

28 more elements

A method for fabricating a semiconductor device, the method comprising:

providing a silicon-on-insulator (SOI) substrate including a buried insulator layer;
forming a semiconductor layer overlying the SOI substrate, the semiconductor layer being doped with a dopant of a first conductivity type;
forming a gate located on the semiconductor layer, the gate including a gate dielectric layer located on the semiconductor layer and a gate conductor layer located on the gate dielectric layer;
forming a source extension region and a drain extension region in the semiconductor layer, the source extension region and the drain extension region contacting the gate dielectric layer, the source extension region and the drain extension region being doped with a dopant of a second conductivity type, which is opposite the first conductivity type;
forming a deep drain region in the semiconductor layer, the deep drain region contacting the drain extension region and abutting the buried insulator layer;
forming a deep source region in the semiconductor layer, the deep source region contacting the source extension region and abutting the buried insulator layer, the deep drain region and the deep source region being doped with a dopant of the second conductivity type;
forming a first metal-semiconductor alloy contact layer using tilted metal formation at an angle tilted towards the source extension region such that the source extension region has a metal-semiconductor alloy contact that abuts the substrate with the first conductive type from the source extension region as a Schottky contact therebetween and the gate shields metal deposition from abutting the deep drain region, wherein the forming the first metal-semiconductor alloy contact layer using tilted metal formation is formed is at the angle θ tilted towards the source extension region such that a size of the angle θ is:
7
⁢
°
<
θ
<
arctan
⁡
(
L
-
2
×
L
1
-
2
×
L
2
-
L
g
h
)
where L is a length between gates, L1 is a width of a first spacer surrounding each side of the gates, L1 is a width of a second spacer surrounding each side of the gates, Lg is a length of the gates;
and h is a height of the gates;
and
forming a second metal-semiconductor alloy contact located on the first metal-semiconductor layer on each of the source extension region and drain extension region.

33 more elements

A silicon-on-insulator (SOI) transistor, comprising:

a substrate including a buried insulator layer with a semiconductor layer formed thereon;
a gate formed on the semiconductor layer with a gate dielectric layer located on the semiconductor layer and a gate conductor layer located on the gate dielectric layer;
a source extension region and a drain extension region formed in the semiconductor layer, the source extension region and the drain extension region contacting the gate dielectric layer;
a deep drain region formed in the semiconductor layer, the deep drain region contacting the drain extension region and abutting the buried insulator layer;
a deep source region in the semiconductor layer, the deep source region contacting the source extension region and abutting the buried insulator layer, the deep drain region;
a first metal-semiconductor alloy contact layer formed using tilted metal formation at an angle tilted towards the source extension region such that the source extension region has a metal-semiconductor alloy contact that abuts the substrate with the first conductive type from the source extension region as a Schottky contact therebetween and the gate shields metal deposition from abutting the deep drain region, wherein the forming the first metal-semiconductor alloy contact layer using tilted metal formation is formed is at the angle θ titled towards the source extension region such that a size of the angle θ is:
7
⁢
°
<
θ
<
arctan
⁡
(
L
-
2
×
L
1
-
L
g
h
)
where L is a length between gates, L1 is a width of a first spacer surrounding each side of the gates, Lg is a length of the gates;
and h is a height of the gates;
and
a second metal-semiconductor alloy contact located on the first metal-semiconductor layer on each of the source extension region and drain extension region.

27 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/548,005Filed 26 Aug 2009
Published: US 2011/0049624 A13 Mar 2011
Granted: 20 Mar 2012
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H10D 86/01
Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless…
H10D 30/0212
Of FETs having insulated gates [IGFET]: using self-aligned silicidation
H10D 30/0323
Comprising silicon, e.g. amorphous silicon or polysilicon: comprising monocrystalline silicon
H10D 30/6717
Characterised by the doping profiles, e.g. having lightly-doped source or drain extensions: the source and the drain regions being asymmetrical