US 8,138,543 B2Granted

Hybrid FinFET/planar SOI FETs

AssigneeInternational Business Machines Corporation

InventorsKangguo Cheng, Bruce B. Doris, Ghavam G. Shahidi

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Abstract

A circuit structure is disclosed which contains least one each of three different kinds of devices in a silicon layer on insulator (SOI): a planar NFET device, a planar PFET device, and a FinFET device. A trench isolation surrounds the planar NFET device and the planar PFET device penetrating through the SOI and abutting the insulator. Each of the three different kinds of devices contain a high-k gate dielectric layer and a mid-gap gate metal layer, each containing an identical high-k material and an identical mid-gap metal. Each of the three different kinds of devices have an individually optimized threshold value. A method for fabricating a circuit structure is also disclosed, which method involves defining portions in SOI respectively for three different kinds of devices: for a planar NFET device, for a planar PFET device, and for a FinFET device. The method also includes depositing in common a high-k gate dielectric layer and a mid-gap gate metal layer, and using workfunction modifying layers to individually adjust thresholds for the various kinds of devices.

Claims16

Dependent claims

A circuit structure, comprising:

least one each of three different kinds of devices in a silicon layer on insulator (SOI):
a planar NFET device, a planar PFET device, and a FinFET device, wherein said FinFET device comprises sidewalls;
a trench isolation penetrating through said SOI and abutting said insulator, wherein said trench isolation surrounds said planar NFET device and said planar PFET device;
wherein each of said three different kinds of devices comprise a high-k gate dielectric layer containing an identical high-k material for all of said three different kinds of devices, and wherein each of said three different kinds of devices comprise a mid-gap gate metal layer containing an identical mid-gap metal for all of said three different kinds of devices, wherein for said FinFET device said high-k gate dielectric layer overlays said sidewalls and said mid-gap gate metal layer is in direct contact with said high-k gate dielectric layer;
individual workfunction modifying layers inbetween said high-k gate dielectric layer and said mid-gap gate metal layer, respectively for said planar NFET device and for said planar PFET device;
and
wherein said circuit structure is characterized as being a combination of a planar CMOS circuit and a FinFET circuit in SOI, wherein said planar CMOS circuit comprises said planar NFET device and said planar PFET device, and wherein each of said three different kinds of devices have an individually optimized threshold value.

4 more elements

A method for fabricating a circuit structure, comprising:

providing a silicon layer on an insulator (SOI);
in said SOI, defining portions respectively for at least one each of three different kinds of devices:
for a planar NFET device, for a planar PFET device, and for a FinFET device;
fabricating a trench isolation that surrounds said portions, wherein said trench isolation penetrates through said SOI abutting said insulator;
removing said trench isolation that surrounds said FinFET portion, wherein exposing sidewalls on said FinFET device;
forming in common a high-k gate dielectric layer and a mid-gap gate metal layer for said three different kinds of devices, wherein for said FinFET device said high-k gate dielectric layer overlays said sidewalls and said mid-gap gate metal layer is in direct contact with said high-k gate dielectric layer;
deploying individual workfunction modifying layers inbetween said high-k gate dielectric layer and said mid-gap gate metal layer, respectively for said planar NFET device and for said planar PFET device;
and
wherein said circuit structure is characterized as combining a planar CMOS circuit with a FinFET circuit, wherein said planar CMOS circuit comprises said planar NFET and said planar PFET device, and individually adjusting threshold values for each one of said three different kinds of devices.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/621,460Filed 18 Nov 2009
Published: US 2011/0115023 A119 May 2011
Granted: 20 Mar 2012
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

H10D 86/011
Manufacture or treatment: comprising FinFETs
H10D 86/215
The substrates comprising an insulating layer on a semiconductor body, e.g. SOI: comprising FinFETs
H10D 30/62
Insulated-gate field-effect transistors [IGFET]: fin field-effect transistors [FinFET]
H10D 84/0167
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their channels