US 8,138,525 B2Granted

Integrated circuit including at least three linear-shaped conductive structures of different length each forming gate of different transistor

AssigneeTela Innovations, Inc.

InventorsScott T. Becker, Michael C. Smayling

Life of this patent

Estimating the term…

Loading patent…

Abstract

A cell of a semiconductor device includes a substrate portion formed to include at least one p-type diffusion region and at least one n-type diffusion region separated by non-active regions. The cell includes a gate electrode level including a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level is fabricated from a respective originating rectangular-shaped layout feature. A width size of the conductive features within a five wavelength photolithographic interaction radius within the gate electrode level is less than a wavelength of light of 193 nanometers. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the cell is greater than or equal to eight. The cell also includes a number of interconnect levels formed above the gate electrode level.

Claims42

Dependent claims

An integrated circuit, comprising:

a gate electrode level region including at least three linear-shaped conductive structures formed to extend lengthwise in a first direction, each of the at least three linear-shaped conductive structures having a lengthwise centerline, the at least three linear-shaped conductive structures positioned according to an equal pitch as measured in a second direction perpendicular to the first direction, such that a distance as measured in the second direction between lengthwise centerlines of different ones of the at least three linear-shaped conductive structures is an integer multiple of the equal pitch, the at least three linear-shaped conductive structures including—
a first linear-shaped conductive structure including a gate portion that forms a gate electrode of a first transistor,
a second linear-shaped conductive structure including a gate portion that forms a gate electrode of a second transistor, and
a third linear-shaped conductive structure including a gate portion that forms a gate electrode of a third transistor,
wherein the first, second, and third linear-shaped conductive structures have different lengths as measured in the first direction.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/572,061Filed 1 Oct 2009 · continuation
Priority: 9 Mar 2006
Published: US 2010/0019285 A128 Jan 2010
Granted: 20 Mar 2012
Term ends: Not estimatedThe source records don’t support an estimate.

Classification26 codes

H10D 84/907
Comprising field effect technology: cMOS gate arrays
G06F 30/39
Circuit design: circuit design at the physical level
G06F 30/392
Circuit design at the physical level: floor-planning or layout, e.g. partitioning or placement
H10D 64/01326
Characterised by the conductor: aspects related to lithography, isolation or planarisation of the conductor

Family

Application60/781,288Us provisional application · filed 9 Mar 2006
Application11/683,402Parent of this continuation · filed 7 Mar 2007
Application12/212,562Parent of this continuation · filed 17 Sep 2008
US 2010/0019285 A1Pre-grant publication · published 28 Jan 2010
US 7,842,975 B2Parent of this continuation
US 7,446,352 B2Parent of this continuation
US 2007/0210391 A1Published application
US 2009/0014811 A1Published application
US 8,138,525 B2This patent

From the US filing history. Foreign family members aren’t listed.