Self-aligned method of forming a semiconductor memory array of floating memory cells with source side erase, and a memory array made thereby

An array of electrically programmable and erasable memory devices comprising:

• a substrate of semiconductor material having a first conductivity type;
• spaced apart isolation regions formed on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions;
• and
• each of the active regions including a plurality of pairs of memory cells, wherein each of the memory cell pairs comprises:
• a first region formed in the substrate,
• a pair of second regions formed in the substrate, with a pair of channel regions each formed in the substrate between the first region and one of the second regions, wherein the first and second regions have a second conductivity type, and wherein each of the channel regions includes a first portion adjacent the first region and a second portion adjacent one of the second regions,
• a pair of electrically conductive floating gates each having a first portion disposed over and insulated from the first region and a second portion disposed over and insulated from one of the channel region first portions for controlling a conductivity thereof, wherein each of the floating gate first portions includes a sloped upper surface and a side surface that meet at an acute edge,
• a block of conductive material disposed over and in electrical contact with the first region, wherein the block of conductive material comprises a first portion that is laterally adjacent to and insulated from the floating gate first portions, and a second portion that extends up and over and is insulated from the floating gate first portions, and
• a pair of electrically conductive control gates each disposed over and insulated from one of the channel region second portions for controlling a conductivity thereof.

A method of forming a semiconductor memory cell, comprising:

• forming first and second regions of a second conductivity type in a substrate of a first conductivity type, wherein the first and second regions are spaced apart from each other with a channel region in the substrate therebetween, and wherein the channel region includes a first portion adjacent the first region and a second portion adjacent the second region;
• forming an electrically conductive floating gate having a first portion disposed over and insulated from the first region and a second portion disposed over and insulated from the channel region first portion for controlling a conductivity thereof, wherein the floating gate first portion includes a sloped upper surface and a side surface that meet at an acute edge;
• forming a block of conductive material disposed over and in electrical contact with the first region, wherein the block of conductive material comprises a first portion that is laterally adjacent to and insulated from the floating gate first portion, and a second portion that extends up and over and is insulated from the floating gate first portion;
• and
• forming an electrically conductive control gate disposed over and insulated from the channel region second portion for controlling a conductivity thereof.

A method of forming an array of electrically programmable and erasable memory devices comprising:

• forming spaced apart isolation regions on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions, wherein the substrate has a first conductivity type;
• and
• forming pairs of memory cells in each of the active regions, wherein the formation of each of the memory cell pairs comprises:
• forming a first region in the substrate,
• forming a pair of second regions in the substrate, with a pair of channel regions each formed in the substrate between the first region and one of the second regions, wherein the first and second regions have a second conductivity type, and wherein each of the channel regions includes a first portion adjacent the first region and a second portion adjacent one of the second regions;
• forming a pair of electrically conductive floating gates each having a first portion disposed over and insulated from the first region and a second portion disposed over and insulated from one of the channel region first portions for controlling a conductivity thereof, wherein each of the floating gate first portions includes a sloped upper surface and a side surface that meet at an acute edge;
• forming a block of conductive material disposed over and in electrical contact with the first region, wherein the block of conductive material comprises a first portion that is laterally adjacent to and insulated from the floating gate first portions, and a second portion that extends up and over and is insulated from the floating gate first portions;
• and
• forming a pair of electrically conductive control gates each disposed over and insulated from one of the channel region second portions for controlling a conductivity thereof.