Test structure for detecting via contact shorting in shallow trench isolation regions
AssigneeInternational Business Machines Corporation
InventorsHuilong Zhu, Shih-Fen Huang, Effendi Leobandung
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Abstract
A test structure for detecting void formation in semiconductor device layers includes a plurality of active device areas formed in a substrate, a plurality of shallow trench isolation (STI) regions separating the active device areas, a plurality of gate electrode structures formed across the active device areas and the STI regions, and a matrix of vias formed over the active device areas and between the gate electrode structures. At least one edge of each of a pair of vias at opposite ends of a given one of the STI regions extends at least out to an edge of the associated active device area.
Claims4
A test structure for detecting void formation in semiconductor device layers, comprising:
- a plurality of active device areas formed in a substrate;
- a plurality of shallow trench isolation (STI) regions separating the active device areas;
- a plurality of gate electrode structures formed across the active device areas and the STI regions;
- and
- a matrix of vias formed over the active device areas and between the gate electrode structures;
- wherein at least one edge of each of a pair of vias at opposite ends of a given one of the plurality of STI regions extends at least out to an edge of the associated active device area, wherein the matrix of vias is disposed so as to result in metal fill of a void formed within one of the STI regions, thereby resulting in a short between a pair of the vias disposed at opposite ends of the void.
Dependencies are inferred from the claim text.