Chip package solder interconnect formed by surface tension

A solder self-assembly structure for an IC chip comprising:

• a release layer disposed on a portion of an upper surface of the substrate, laterally spaced from a via in the substrate;
• a barrier layer metallization (BLM) disposed in a first part over a portion of the substrate including a via, and in a second part over the release layer, wherein a surface of the substrate is exposed between the first portion and the second portion of the BLM;
• and
• a solder structure disposed over the first and second portions of the BLM and the exposed surface of the substrate disposed there between;
• wherein the release layer is the same size or smaller than the solder structure.

An integrated circuit (IC) chip package comprising:

• a plurality of solder self-assembly structures, each structure comprising:
• a release layer disposed on a portion of an upper surface of a substrate, laterally distanced from a via in the substrate;
• a barrier layer metallization (BLM) disposed in a first part over the substrate including a via, and in a second part over the release layer, wherein a surface of the substrate is exposed between the first portion and the second portion of the BLM;
• and
• a solder structure disposed over the first and second portions of the BLM and the exposed surface of the substrate disposed there between,
• wherein the release layer further comprises one of a patterned release layer and a gap, and
• wherein the plurality of solder self-assembly structures are arranged such that the release layer on each solder self-assembly structure is oriented radially outwardly relative to a center of the IC chip.