Semiconductor devices having pFET with SiGe gate electrode and embedded SiGe source/drain regions and methods of making the same

A method of making a semiconductor device, the method comprising:

• forming a first gate stack on a substrate at a pFET region, wherein the first gate stack comprises a first gate electrode material overlying a gate dielectric material, wherein the first gate electrode material comprises SiGe;
• forming a second gate stack on the substrate at an nFET region;
• forming spacer structures and implanting ions into source/drain regions of the substrate at the nFET and pFET regions;
• etching the source/drain regions of the substrate at the pFET region and the first gate electrode material of the first gate stack at the pFET region, wherein source/drain recesses are formed by etching the source/drain regions of the substrate at the pFET region, and wherein at least part of the first gate electrode material is removed by the etching from the first gate stack to form a gate electrode recess;
• forming a SiGe material in the source/drain recesses and in the gate electrode recess at the pFET region
• forming a tensile-stress-inducing mask layer over the substrate, the spacer structures, and the gate stacks;
• and
• removing the tensile-stress-inducing mask layer from the pFET region, while retaining the tensile-stress-inducing mask layer over the nFET region using a first patterned mask layer, wherein the tensile-stress-inducing mask layer comprises a material selected from the group consisting of nitride, high-k dielectric, HfO2, Al2O3, ZrO2, HfSiO, HfSiN, AlN, La2O3, TiO2, Ta2O5, and combinations thereof.

A method making a semiconductor device, the method comprising:

• forming a first gate stack on a substrate at a pFET region, wherein the first gate stack comprises a first gate electrode material overlying a gate dielectric material, wherein the first gate electrode material comprises SiGe;
• forming a second gate stack on the substrate at an nFET region;
• forming spacer structures and implanting ions into source/drain regions of the substrate at the nFET and pFET regions;
• etching the source/drain regions of the substrate at the pFET region and the first gate electrode material of the first gate stack at the pFET region, wherein source/drain recesses are formed by etching the source/drain regions of the substrate at the pFET region, and wherein at least part of the first gate electrode material is removed by the etching from the first gate stack to form a gate electrode recess;
• forming a SiGe material in the source/drain recesses and in the gate electrode recess at the pFET region
• forming a tensile-stress-inducing mask layer over the substrate, the spacer structures, and the gate stacks;
• removing the tensile-stress-inducing mask layer from the pFET region, while retaining the tensile-stress-inducing mask layer over the nFET region using a first patterned mask layer;
• implanting boron ions after the growing of the SiGe material;
• annealing the nFET and pFET regions after the implanting of boron ions;
• and
• removing the tensile-stress-inducing mask layer from the nFET region while shielding the pFET region with a second patterned mask layer.

A method of making a semiconductor device, the method comprising:

• forming a first gate stack on a substrate at a pFET region, wherein the first gate stack comprises a first gate electrode material overlying a gate dielectric material, wherein the first gate electrode material comprises SiGe;
• forming a second gate stack on the substrate at an nFET region;
• forming spacer structures and implanting ions into source/drain regions of the substrate at the nFET and pFET regions, wherein the forming spacer structures and implanting ions step comprises:
• forming low temperature oxide (LTO) spacers on sidewalls of the first and second gate stacks;
• implanting ions into the source/drain regions of the substrate at the nFET and pFET regions to a first implanting depth in alignment with the LTO spacers;
• forming a LTO layer over the substrate, the first gate stack, and the second gate stack;
• forming nitride spacers on sidewalls of the LTO spacers, such that the LTO spacers are located between the gate stacks and the nitride spacers and such that the LTO layer is located between the nitride spacer and the substrate;
• and
• implanting ions into the source/drain regions of the substrate at the nFET and pFET regions to a second implanting depth in alignment with the nitride spacers, the second implanting depth being greater than the first implanting depth;
• etching the source/drain regions of the substrate at the pFET region and the first gate electrode material of the first gate stack at the pFET region, wherein source/drain recesses are formed by etching the source/drain regions of the substrate at the pFET region, and wherein at least part of the first gate electrode material is removed by the etching from the first gate stack to form a gate electrode recess;
• forming a SiGe material in the source/drain recesses and in the gate electrode recess at the pFET region
• forming a tensile-stress-inducing mask layer over the substrate, the spacer structures, and the gate stacks;
• and
• removing the tensile-stress-inducing mask layer from the pFET region while retaining the tensile-stress-inducing mask layer over the nFET region using a first patterned mask layer.

A method of making a semiconductor device, the method comprising:

• forming a first gate stack on a substrate at a pFET region, wherein the first gate stack comprises a first gate electrode material overlying a gate dielectric material, wherein the first gate electrode material comprises SiGe;
• forming a second gate stack on the substrate at an nFET region, wherein the second gate stack also comprises the first gate electrode material overlying the gate dielectric material;
• forming spacer structures and implanting ions into source/drain regions of the substrate at the nFET and pFET regions;
• forming a mask layer covering the nFET region, wherein forming the mask layer comprises
• forming a first oxide layer over the substrate, the spacer structures, and the gate stacks,
• forming a nitride layer over the first oxide layer, and
• removing the nitride layer and the first oxide layer from the pFET region while retaining the nitride layer and the first oxide layer over the nFET region using a first patterned mask layer;
• etching the source/drain regions of the substrate at the pFET region and the first gate electrode material of the first gate stack at the pFET region, wherein source/drain recesses are formed by the etching in the source/drain regions of the substrate at the pFET region, and wherein at least part of the first gate electrode material is removed by the etching from the first gate stack to form a gate electrode recess, wherein the etching process while etching the source/drain regions is at least partially selective against etching oxide and nitride materials so that the nFET region is shielded by the nitride layer and so that the spacer structure of the pFET region at least partially remains;
• and
• epitaxially growing a SiGe material in the source/drain recesses and in the gate electrode recess at the pFET region.

A method of making a semiconductor device, the method comprising:

• forming a first gate stack on a substrate at a pFET region, wherein the first gate stack comprises a first gate electrode material overlying a gate dielectric material;
• forming a second gate stack on the substrate at an nFET region;
• forming spacer structures and implanting ions into source/drain regions of the substrate at the nFET and pFET regions;
• etching the source/drain regions of the substrate at the pFET region and the first gate electrode material of the first gate stack at the pFET region, wherein source/drain recesses are formed by etching the source/drain regions of the substrate at the pFET region, and wherein at least part of the first gate electrode material is removed by the etching from the first gate stack to form a gate electrode recess;
• forming a SiGe material in the source/drain recesses and in the gate electrode recess at the pFET region;
• forming a tensile-stress-inducing mask layer over the substrate, the spacer structures, and the gate stacks;
• removing the tensile-stress-inducing mask layer from the pFET region, while retaining the tensile-stress-inducing mask layer over the nFET region using a first patterned mask layer;
• implanting boron ions after the growing of the SiGe material;
• annealing the nFET and pFET regions after the implanting of boron ions;
• and
• removing the tensile-stress-inducing mask layer from the nFET region while shielding the pFET region with a second patterned mask layer.

A method of making a semiconductor device, the method comprising:

• forming a first gate stack on a substrate at a pFET region, wherein the first gate stack comprises a first gate electrode material overlying a gate dielectric material;
• forming a second gate stack on the substrate at an nFET region, wherein the second gate stack also comprises the first gate electrode material overlying the gate dielectric material;
• forming spacer structures and implanting ions into source/drain regions of the substrate at the nFET and pFET regions;
• forming a mask layer covering the nFET region, wherein forming the mask layer comprises:
• forming a first oxide layer over the substrate, the spacer structures, and the gate stacks,
• forming a nitride layer over the first oxide layer, and
• removing the nitride layer and the first oxide layer from the pFET region while retaining the nitride layer and the first oxide layer over the nFET region using a first patterned mask layer;
• etching the source/drain regions of the substrate at the pFET region and the first gate electrode material of the first gate stack at the pFET region, wherein source/drain recesses are formed by the etching in the source/drain regions of the substrate at the pFET region, and wherein at least part of the first gate electrode material is removed by the etching from the first gate stack to form a gate electrode recess, wherein the etching process while etching the source/drain regions is at least partially selective against etching oxide and nitride materials so that the nFET region is shielded by the nitride layer and so that the spacer structure of the pFET region at least partially remains;
• and
• epitaxially growing a SiGe material in the source/drain recesses and in the gate electrode recess at the pFET region.