Metal high dielectric constant transistor with reverse-T gate

A non-transitory computer readable medium encoded with program instructions for execution by a processor, which when executed by the processor, cause at least one processing tool to fabricate a transistor, the program instructions comprising instructions for performing the steps of:

• providing a silicon layer;
• forming a first layer on the silicon layer, the first layer comprising a high dielectric constant material;
• forming a second layer on the first layer, the second layer comprising a metal or metal alloy;
• forming a third layer on the second layer, the third layer comprising silicon or polysilicon;
• etching, by the at least one processing tool, the first, second, and third layers so as to form a gate stack;
• and
• after etching the first, second, and third layers, etching the third layer of the gate stack without etching the first and second layers of the gate stack, so as to substantially reduce the width of the third layer of the gate stack.

A non-transitory computer readable medium encoded with program instructions for execution by a processor, which when executed by the processor, cause at least one processing tool to fabricate a transistor, the program instructions comprising instructions for performing the steps of:

• providing a silicon layer;
• forming a first layer on the silicon layer, the first layer comprising a high dielectric constant material;
• forming a second layer on the first layer, the second layer comprising a metal or metal alloy;
• forming a third layer on the second layer, the third layer comprising silicon or polysilicon;
• etching, by the at least one processing tool, the third layer without etching the first and second layers;
• after etching the third layer, depositing a spacer layer;
• etching, by the at least one processing tool, the spacer layer so as to form a spacer on sidewalls of the third layer;
• and
• after etching the spacer layer, using the spacer and the third layer as a mask to etch the first and second layers without etching the third layer, so as to form a gate stack comprising the first, second, and third layers, with a lateral extent of the second layer of the gate stack being substantially greater than a lateral extent of the third layer of the gate stack.