Integrated circuit system with high voltage transistor and method of manufacture thereof

A method of manufacture of an integrated circuit system comprising:

• providing a semiconductor substrate having an active region, implanted with impurities of a first type at a first concentration;
• forming an isolation region around the active region including forming a shallow trench isolation;
• forming a parasitic transistor by applying a gate electrode, implanted with impurities of a second type at a second concentration, over the active region and the isolation region including applying a layer of poly-silicon on a gate oxide layer;
• and
• applying an isolation edge implant, with the impurities of the first type at a third concentration that is greater than or equal to the second concentration, for suppressing the parasitic transistor including increasing a threshold voltage of the parasitic transistor.

An integrated circuit system comprising:

• a semiconductor substrate having an active region, implanted with impurities of a first type at a first concentration;
• an isolation region around the active region;
• a parasitic transistor formed by a gate electrode, implanted with impurities of a second type at a second concentration, over the active region and the isolation region;
• and
• an isolation edge implant, with the impurities of the first type at a third concentration that is greater than or equal to the second concentration, for suppressing the parasitic transistor.